LPDDR5(X) protocol training

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LPDDR5(X) protocol training

  • Course Duration: 17 hours
  • 4.6 Star (Rating)
  • 5000+ (Student Enrolled till Now)
About Course
  1. WCK Clocking
  2. Initialization and Training
  3. LPDDR5 State Diagram
  4. Mode Register Definition
  5. LPDDR5 Operations
  6. Command Constraint and AC timing
  7. AC Timing

Die configuration, Package ballout, Pin Definition

 
Demo Videos

Course videos

Unit numberTopicDuration (mins)
1LPDDR5 enhancements28:35
2Overview08:12
3Pad definitions and description08:45
4Bank architecture15:52
5Addressing20:25
6Speed grades04:28
7Burst Sequence05:26
8WCK Clocking09:20
9Simplified LPDDR5 State Diagram08:52
10Mode register summary - LPDDR5, LPDDR5X17:59
11Mode register definition (MR0, MR1)12:33
12Mode register definition (MR3 - MR20)22:28
13Mode register definition (MR38 - MR72)28:23
14Command truth table13:59
15WCK2CK synchronization22:35
16Row operation18:37
17burst read operation11:51
18burst write operation09:56
19read write latency07:42
20write recovery time03:58
21masked write operation07:05
22Refresh operation34:55
23Refresh command timing constraints10:20
24Optimized refresh11:40
25Self refresh operation11:37
26Partial array self refresh04:47
27Power down25:07
28Deep sleep mode09:56
29Other operation11:58
30Frequency set point26:43
31DDR ODT basics00:33:12
32On die termination for CA bus, Data bus, and WCK_t/c33:06
33Non-target DRAM ODT18:09
34Asynchronous NT ODT19:19
35NT ODT - Rank2Rank write to read timing diagram05:08
36NT ODT setting by MRW command04:30
37NT ODT behavior unification05:27
38Input clock stop and frequency change08:52
39VREF Current generator05:33
40Thermal Offset05:37
41Temparature sensor07:49
42Multi purpose command03:03
43tWCK2DQ interval oscillator.16:11
44Interval Oscillator matching error04:05
45WCK2DQX Oscillator Readout timing04:06
46DVFS16:36
47Data Copy Low power function14:27
48Write X Operation10:48
49Initialization and training14:48
50Dual VDD2 rail setting06:30
51ZQ calibration basics00:11
52Training - ZQ calibration22:04
53ZQ calibration - Command based calibration17:48
54ZQ calibration - ZQ resistor sharing07:36
55ZQ calibration - ZQ Reset03:10
56ZQ calibration - Multi die considerations10:41
57Command bus training mode1, Physical mode registers22:01
58Command bus training mode1 for single and multi rank systems25:56
59Command bus training mode2 sequence10:35
60Command bus training mode 2 sequence for single and multi rank systems16:31
61WCK2CK Leveling11:03
62Duty Cycle Adjuster10:00
63Read Duty Cycle Adjuster04:09
64Duty Cycle monitor08:54
65Read DQ Calibration13:44
66WCK DQ Training12:50
67WCK DQ Training07:27
68RDQS Toggle mode10:47
69Read Write based WCK RDQS T-training05:46
70Rx Offset Calibration training02:38
71Post Package Repair10:07
72Enhancements20:03
73Refresh management command12:21
74Refresh management threshold13:58
75Refresh management enhancement05:43
76Decision feedback Equalization12:42
77Link ECC06:22
78Link ECC Check matrix22:08
79Single ended mode for clock writeclock and rdqs12:03
80Enhanced WCK always on mode05:50
81Pre-emphasis for DQ output02:46
82Rank to rank AC parameter and common contraint timing08:27
83Read to Write timing Command constraint03:56
84Auto Precharge command timing constraints04:37
85CAS command timing constraints14:07
86Training related timing constraints07:19
87Rank to rank command timing constraints05:54

 

Curriculum

Features
Functional Description
Pad Definition and Description
Pin per byte
LPDDR5/LPDDR5X Bank Architecture
LPDDR5 Address Translation Table
Bank architecture transition
Burst Operation
LPDDR5 SDRAM Addressing
Speed Grade
Burst Sequence
Power-up, Initialization and Power-off Procedure
Voltage Ramp and Device Initialization
Dual VDD2 Rail setting (MR13 OP[7]) and its change
Reset Initialization with Stable Power
Power-off Sequence
Uncontrolled Power-off Sequence
Training
ZQ Calibration
ZQ Reset
Multi-die Package Considerations
ZQ External Resistor, Tolerance, and Capacitive Loading
Flow Chart Examples
Command Bus Training
Three Physical Mode Register
Command Bus Training Mode1
Command Bus Training Mode1 (FSP with DVFSQ enable)
Command Bus Training Mode2
Command Bus Training Mode2 (FSP with DVFSQ enable)
CA VREF Training
DQ VREF Training
WCK2CK Leveling
Write-leveling called in LPDDR4
Duty Cycle Adjuster (DCA)
Duty Cycle Adjuster Range
Relationship between WCK waveform and DCA Code Change
The relationship between DCA Code Change and DQ output/RDQS timing
Read DCA (Duty Cycle Adjuster)
Duty Cycle Monitor (DCM)
READ DQ Calibration
WCK-DQ Training
RDQS Toggle Mode
Enhanced RDQS Training Mode
Read/Write-based WCK-RDQS_t Training
Rx Offset Calibration Training
Mode Register Assignment and Definition
Mode Register Assignment and Definition in LPDDR5
Mode Register Assignment and Definition in LPDDR5X
Mode Register Definition
Truth Table
Command Truth Table
WCK Operation
WCK2CK Synchronization operation
Row Operation
Read/Write Operation
Refresh Operation
Other Operation
Reliability & Power-optimization
Dynamic Voltage and Frequency Scaling (DVFS)
Data Copy Low Power Function
Write X operation
Post Package Repair (PPR)
Refresh Management Command
Refresh Management Enhancement (ARFM)
Decision Feedback Equalization (DFE)
Link ECC
Single-ended mode for Clock, Write Clock, and RDQS
Enhanced WCK Always On Mode
Pre-Emphasis for DQ output
Rank to Rank AC Parameter
Effective Burst Length (BL/n) Definition
Command Timing Constraints
Read to Write Timing (tRTW)
Auto Precharge Command Timing Constraints
CAS Command Timing Constraints
Training Related Timing Constraints
MRR/MRW Timing Constraints
Rank to Rank Command Timing Constraints
Core AC Timing Parameters by Speed Grade
Mode Register Assignment and Definition in LPDDR5
Core AC Timing Parameters for LPDDR5X

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Course Highlights

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  • Multiple mock interviews
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DFT Training FAQ

  1. Course presentations for all topics
  2. Session notes
  3. Lab documents with detailed steps
  4. User guides

Course does not have any pre-requisites. However any exposure to Digital design, VLSI design flow is an added advantage.

  • Each session of course is recorded, missed session videos will be shared

  1. Yes, You will have option to view the recorded videos of course for the sessions missed
  2. You will have option to repeat the course any time in next 1 year

  1. Yes, Course fee also includes support for doubt clarification sessions even after course completion
  2. You have option to mail you queries
  3. Option to meet in person to clarify doubts