DFT Training
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DFT Training
- Course Duration: 119 Hours
- 4.8 Star (Rating)
- 20000+ (Student Enrolled till Now)
About Course
DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted for developing and applying tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.
DFT Training will focus on all aspects of testability flow including DFT basics, various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.
As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.
DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.
MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.
Demo Videos
| Unit Number | Topic | Duration (Mins) |
| 1 | What is DFT Manufacturing Defects, Why Testing Major Challenges in DFT | 52 |
| 2 | Fault Models, Types of Test Logic Insertion | 41 |
| 3 | Assignment Questions | 18 |
| 4 | Difference between pin, port and pad & clock gating | 39 |
| 5 | Disadvantages of clock gating cell (and gate), Integrated clock gating cell (ICG) | 25 |
| 6 | Need of DFT | 47 |
| 7 | Yield, Defect, Fault and error & DFT architecture | 73 |
| 8 | Scan Insertion | 69 |
| 9 | Calculating over all Test time post scan insertion | 21 |
| 10 | Full sacn vs Partial scan, Types of scan cells | 51 |
| 11 | Comparision of various scan cells, Scan chain operation | 42 |
| 12 | Problems with scan designs | 22 |
| 13 | Clock controllability DRC | 115 |
| 14 | Assignment answers discussions | 24 |
| 15 | Reset controllability DRC | 26 |
| 16 | Tristate buffer DRC, potential race condition | 44 |
| 17 | X source DRC, Feedback loop DRC | 30 |
| 18 | Deciding the no.of scan chains and scan chain length | 23 |
| 19 | Bus contention, Top down apprach, Bottom up appraoch | 27 |
| 20 | Inputs and outputs of scan, Scan chain reorder | 56 |
| 21 | Edge mixing and domain mixing | 46 |
| 22 | Practical Explanation of scan insertion | 25 |
| 23 | Pre-existing scan chains | 22 |
| 24 | Scan compression and its need | 87 |
| 25 | Decompressor, Compression ratio, Compressor | 18 |
| 26 | Bypass, Pipeline flops in compressor | 63 |
| 27 | EDT waveform, masking logic | 29 |
| 28 | Lock up latches, EDT insertions in hierarchical scan | 23 |
| 29 | EDT DRCs | 20 |
| 30 | Methods to fix DRCs, ATPG introduction | 38 |
| 31 | D algorithm | 8 |
| 32 | Other algorithms, Fault model | 29 |
| 33 | Fault categories | 40 |
| 34 | Coverage, Untestable faults, Flow of ATPG | 46 |
| 35 | Fault classes | 55 |
| 36 | ATPG Untestable (AU) class | 62 |
| 37 | Other AU faults, Untestable faults | 11 |
| 38 | Assignment answers discussion and doubt clarrifications | 30 |
| 39 | Patterns classification chain, serial, parallel | 16 |
| 40 | Pattern classification (based on format and category) | 73 |
| 41 | ATPG practicals | 33 |
| 42 | Simulations | 46 |
| 43 | Practicals of ATPG TDF and simulations | 87 |
| 44 | Simulation mismatch debug | 36 |
| 45 | Doubt clarifications, Assignment questions | 27 |
| 46 | OCC part 1 | 67 |
| 47 | OCC part 2 | 12 |
| 48 | Doubt clarification and assignment discussions | 12 |
| 49 | Doubt clarification, Assignment discussions | 63 |
| 50 | ATPG IDDQ theory | 8 |
| 51 | IDDQ lab | 17 |
| 52 | Path Delay Fault Model (PDF) | 53 |
| 53 | JTAG introduction, Boundary Scan | 20 |
| 54 | Instructions (Mandatory + Optional) | 17 |
| 55 | JTAG network, comparison between various standards | 20 |
| 56 | BSDL | 33 |
| 57 | Assignment answers discussion | 21 |
| 58 | JTAG TAP architecture | 58 |
| 59 | JTAG TAP Controller (16 state FSM) | 23 |
| 60 | Memory Basics, Memory architecture | 16 |
| 61 | Memory Faults | 52 |
| 62 | Memory Faults (Contd...) | 15 |
| 63 | Zero-One algorithm and Checkerboard algorithm | 14 |
| 64 | March Algorithms (MATS, MATS+, MATS++, MarchX, March C) | 28 |
| 65 | Algorithms supported by mentor tools | 56 |
| 66 | Tessent MBIST | 25 |
| 67 | Comparision between JTAG and IJTAG | 29 |
| 68 | TSDB flow explanation | 80 |
| 69 | Lab MBIST insertion | 66 |
| 70 | TSDB output directory explanation, MBIST simulations | 58 |
| 71 | Lab | 64 |
| 72 | Scan Wrappers | 84 |
| 73 | Lab3 (MBIST, EDT OCC insertion) | 21 |
| 74 | Lab3 (Scan, ATPG, Simulation, MBIST patterns on netlist) | 21 |
| 75 | Lab4 (MBIST, EDT OCC insertion) | 37 |
| 76 | Lab4 remaining topics | 50 |
| 77 | Level 4 projects THY | 50 |
Curriculum
| ASIC & VLSI Design Flow |
| Session covering complete flow overview from product requirements to Post silicon validation. |
| Advanced Digital Design |
| 2 weeks dedicated course focusing on all aspects of Digital design. |
| www.vlsiguru.com/digital-design-complete |
| Verilog programming basics |
| 3 Weeks of Verilog training covering all the aspects of Verilog required for DFT engineer |
| This course is done in parallel with Advanced Digital design course |
| Linux OS |
| 1 week training on Linux OS and hands on |
| TCL Scripting |
| 1 week training on TCL scripting for flow automation |
| DFT Basics |
| SoC Scan architecture overview |
| Types of Scan |
| ATPG DRC Debug |
| ATPG Simulation Mismatch Debug |
| JTAG |
| MemoryBIST |
| Scan and ATPG |
| Test compression technigues |
| Hierarchical Scan Design |
| Full SOC flow - DFT |
| DFT Architecture and Basics |
| Test Plan |
| Different DFT schemes |
| Comparison between Functional and DFT Vectors |
| Understanding of SCAN Insertion |
| Scan methodology |
| Types of Scan |
| Top-down and Bottom-up Approach |
| Scan insertion Flow |
| Scan insertion Scripts |
| Multiple Clock domains |
| Design Rule Checking |
| Pre-DRC and Post DRC |
| Lock up and Terminal lockup latches |
| Hands-on Scan insertion |
| Assignments |
| Introduction to compression |
| Compression Architecture |
| Decompressor and Compactor |
| Compression Ratio |
| DRC Analysis |
| Modular Compression |
| X-Masking logic |
| Hands-on Compression |
| Assignments |
| Scan insertion with compression |
| On-chip clocking for at-speed testing |
| Hierarchical Scan Design |
| Bypass mode |
| Hands on Scan and compression |
| Interaction session scan and compression |
| Memory faults |
| Algorithms |
| Diagnostic mode |
| ATPG Overview |
| Different types of Faults |
| Types of fault models |
| DRC analysis |
| Test Coverage and Fault Coverage |
| Coverage improvement Analysis |
| Chain and Capture patterns |
| Assignments |
| Simulations- No-timing |
| At speed fault model (In detail) |
| Understanding Transition fault ATPG |
| Two pulse generator |
| Test procedure |
| Launch on capture and Launch on Shift |
| Top-off Pattern generation |
| Path delay |
| Introduction to JTAG |
| JTAG State Machine |
| Boundary Scan |
| Different instructions |
| Industry Standard Project |
| Revision |
| Mock Interview |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Dedicated Trainer Accessible On Phone / Email / Whatsapp
- Trainer Exp: 15 Years
Course Highlights
- 1-1 mentor support
- Mentor guidance support for assignments
- Multiple mock interviews
- Dedicated live support sessions over weekends
TESTIMONIALS
What Our Students Says About Inskill
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I recently completed the Functional Verification course at VLSIGuru, and I must say it was an exceptional training experience.
The course content was comprehensive, covering all essential aspects of functional verification.
The instructors were highly knowledgeable and provided clear explanations,making complex concepts easy to understand.
The practical hands-on exercises and real-world examples greatly enhanced my learning and problem-solving skills.
The course structure was well-organized, allowing for a smooth progression from fundamentals to advanced topics.
Overall, VLSIGuru's Functional Verification course has equipped me with the necessary skills and confidence to excel in the field.
Highly recommended!
I have taken training at VLSIGURU for Design and functional verification course through online,
where i got more practical knowledge then usual syllabuses.
I was very much satisfied learning at this training institute.
Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience
which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period.
every sessions recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provide online access as well.
This institute has highly well experienced real time working professionals as trainers.
thanks to VLSIGURU institute.
I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.
The admins are very much co-operative and understandable and help you throughout the course.
The concepts taught are in a very simplified manner and every lecture is recorded.
Very much satisfied will recommend to any VLSI enthusiast
FAQ
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
Institute is driven by philosophy of ‘Quality education at affordable fee’. Education should be affordable to majority of the people. Even otherwise basic courses like Digital Design, Verilog, SV, UVM, UNIX and Scripting all together can’t cost 1 lakh+. These are just languages and some projects.
- Basic exposure to digital design concepts