In modern VLSI chip design, the journey doesn’t stop at writing RTL. In fact, the RTL (Register Transfer Level) representation is just the beginning. It’s a high-level functional model that describes what a design should do, not how it will be physically implemented on silicon. That transformation from abstract logic to a manufacturable silicon layout is handled by the Physical Design Flow, a critical stage in ASIC and FPGA development.

In this blog, we break down what happens after RTL, exploring every major step in the physical design flow, from synthesis to GDSII, while explaining key concepts, tools, challenges, and best practices. Whether you’re an aspiring VLSI engineer, student, or professional bridging the gap between RTL and silicon, this guide will give you a solid grasp of the journey ahead.

1. RTL Verification

Before diving into physical design, RTL must be thoroughly verified to ensure correctness. This isn’t technically in the physical design flow, but it’s a gate check because physical implementation depends on verified logic.

• Functional simulation: Running testbenches against RTL.
• Code coverage & assertion checks: Ensuring all scenarios are exercised.
• Formal verification: Proving functional equivalence in some cases.
  
  

Only after verification, confidence is high, do we proceed to the next stage,  logic synthesis.

2. Logic Synthesis

Once RTL is verified, it is synthesized into a gate-level netlist with the help of synthesis tools such as Synopsys Design Compiler or Cadence Genus.

Purpose

Transform high-level behavioral descriptions (Verilog/VHDL) into a structural representation built from standard cell libraries.

Key Tasks

• Technology mapping: Translating RTL constructs into specific logic cells (AND, OR, flip-flops) available in the target library.
• Optimization: Balancing between area, timing, and power based on constraints provided by the designer.
• Constraint enforcement: Applying timing, power and area constraints via Synopsys SDC format.
  
  

Output

• A gate-level netlist (.v or .edf file)
• Reports on area, timing and power
• Constraint files that feed into physical design

3. Floorplanning

Floorplanning is the stage where designers decide how to physically arrange logic blocks on the chip.

Why It Matters

A good floorplan reduces interconnect congestion, improves timing, and simplifies placement and routing later in the flow.

Tasks in Floorplanning

• Defining core area: The usable area inside the chip’s bounding box.
• Macro placement: Placing large blocks like memories and DSP blocks.
• Aspect ratio & power planning: Allocating regions for power grids and I/O pads.
  
  

Deliverables

• A floorplan layout
• Power distribution network plan (PDN)
• Block placement guideline
  
  

4. Placement

After floorplanning, the gate-level netlist moves to placement, where each standard cell is assigned a physical location.

Objectives

• Minimize total wire length
• Achieve timing closure
• Respect design rules
  
  

Important Steps

• Global placement: Rough positioning of cells in rows
• Legalization: Adjusting to legal positions without overlap
• Detailed placement: Final refinement
  
  

Placement tools (e.g., Cadence Innovus, Synopsys ICC2) use heuristics to optimize timing, power, and area simultaneously.

5. Clock Tree Synthesis (CTS)

Clocks drive synchronous design. But after placement, clocks still need careful routing to ensure all flip-flops receive the clock simultaneously.

What CTS Does

• Builds a balanced clock tree
• Minimizes clock skew (difference in arrival time between endpoints)
• Controls clock insertion delay
  
  

Challenges

• Balancing skew versus latency
• Power impact of clock buffers
• Managing multiple clock domains
  
  

Proper CTS ensures the design meets timing across all corners.

6. Routing

With placement and clocks in place, it’s time to route, i.e., lay down the actual metal wires that connect every cell pin.

Types of Routing

• Global routing: Determines routes at a high level
• Detailed routing: Assigns exact tracks and layers
  
  

Goals

• Respect spacing and width DRC (Design Rule Check) constraints
• Minimize crosstalk and signal integrity issues
• Maintain timing targets
  
  

Routing is perhaps the most complex step because real silicon has physical properties — resistance, capacitance, interference — that must be respected.

7. Physical Verification

After routing, the design must be checked for manufacturability. Two major checks are performed:

Design Rule Check (DRC)

DRC verifies the layout against foundry design rules such as:

• Minimum spacing
• Minimum width
• Via rules
• Metal density
  
  

Violations here can lead to manufacturing faults.

Layout vs. Schematic (LVS)

LVS compares the layout netlist to the original gate-level netlist to ensure:

• No missing or extra connections
• Correct component representation
  
  

Physical verification flows are done using tools like Mentor Calibre or Synopsys IC Validator.

8. Static Timing Analysis (STA): Timing Closure

With layout and connections complete, the design undergoes Static Timing Analysis (STA) to check:

• Setup and hold times
• Path delays through logic and interconnect
• Timing across corners (process, voltage, temperature)
  
  

Why STA Is Essential

Physical delays vary due to wire resistance/capacitance and cell characteristics. STA computes the worst-case timing paths without simulation.

Actions After STA

If paths fail timing, designers may:

• Resynthesize logic
• Re-place/re-route cells
• Adjust constraints
• Add buffers or restructure paths
  
  

Tools such as Synopsys PrimeTime are commonly used here.

9. Power Analysis and Optimization

Performance isn’t the only goal, power matters!

Power Checks Include

• Dynamic power: Switching activity
• Leakage power: Idle transistors
• IR Drop & Electromigration: Power supply integrity
  
  

Techniques

• Clock gating
• Power gating
• Multi-Vt library usage
• Late power optimization passes
  
  

Tools like Apache RedHawk or PrimePower analyze and guide power fixes.

10. Sign-off and Tape-out

After design passes all checks (DRC/LVS/STA/Power), it’s ready for sign-off, meaning engineering teams, RTL, physical, verification and sign-off engineers — review data.

Tape-out

The final result, a verified GDSII/OASIS layout, is sent to the foundry to manufacture the silicon.

Tape-out marks the end of the design cycle and the beginning of fabrication.

Why Physical Design Matters

The physical design flow is where logic meets reality. It’s a demanding phase where:

• Abstract constructs become real silicon structures
• Electrical effects, manufacturing rules and performance targets all collide
• Engineers use both art and tool-driven automation to achieve an optimal result
  
  

Failing to adequately perform physical design can result in chips that don’t meet performance targets, waste area, consume too much power, or aren’t manufacturable.

Final Thoughts

Understanding what happens after RTL is a must for anyone pursuing a VLSI or ASIC/FPGA design career. Today’s industry demands engineers who can connect code to silicon, leverage automation while mastering concepts like timing, placement, routing, verification and power, not just writing RTL.

Whether you aim to be a physical design engineer, STA expert, verification engineer, or ASIC design lead, mastering the physical design flow is foundational. This deep dive equips you to understand real chip design challenges and prepares you for advanced topics like DFT (Design for Test), PPA (Power, Performance, Area) optimization, and advanced node challenges at 7nm and beyond.