VLSI Training
AMBA CHI Training
AMBA CHI Training AMBA protocol training is focused on all aspects of cache coherency, cache state model and channels,switching, register and reset, initialization, configuration, etc.Course also focus on power management, security, performance, etc.
- 29 HoursCourse Duration
- 62 SessionsRecorded & Live
- 4.6/5Learner Rating
- 500+Enrolled Learners
Course Overview
Course Overview
AMBA CHI Training AMBA protocol training is focused on all aspects of cache coherency, cache state model and channels,switching, register and reset, initialization, configuration, etc.
Course also focus on power management, security, performance, etc.
Detailed Syllabus
15 modules- ACE versus CHI
- Cache, System memory, secondary memory
- Page tables – Virtual and Physical address
- Cache, Cache line, Cache coherence, Snoop, CCI
- Hardware and software managed coherency
- MOESI
- 7 States of Cache line
- Architecture overview – RN, HN, SN
- Architecture layers
- Architecture layers
- Topology
- Transaction classification
- Component naming
- Channels overview
- Channel mapping for different nodes
- Channel mapping for different nodes
- Channel fields - opcodes
- Transaction structure
- Transaction identifier fields
- Logical Processor Identifier
- Ordering
- Address, Control, and Data
- Data transfer
- Request Retry
- System address map
- Node ID
- Target ID determination
- Network layer flow examples
- Flit
- Interface activation and deactivation
- Transaction flow for write, read, dataless, CMO, Non-CMO
- Combined write transactions, Atomic transactions
- Misc. transactions
- Transaction retry sequence
- Snoop transactions
- Response types
- Ordering
- Transaction attributes
- Forwarding snoop transactions
- Exclusive accesses
- Cache line states
- Request types
- Snoop request types
- Request types and corresponding Snoop requests
- Response types
- Silent cache state transitions
- Cache state transitions at a Requester
- Cache state transitions at a Snoopee
- Returning Data with Snoop response
- Do not transition to SD
- Hazard conditions
- Read transaction flows
- Dataless transaction flows
- Write transaction flows
- Atomic transaction flows
- Stash transaction flows
- Hazard handling examples
- Overview
- Exclusive monitors
- Exclusive transactions
- Write with Stash hint
- Independent Stash request
- Stash target identifiers
- Stash messages
- DVM transaction flow
- DVM Operation types
- DVM Operations
- Error types
- Error response fields
- Errors and transaction structure
- Error response use by transaction type
- Poison
- Data Check
Session-wise Content
62 sessions · 28h 37m- 1Agenda6m
- 2Need for CHI Protocol55m
- 3Cache coherency46m
- 4Cache line states33m
- 5MOESI state diagram51m
- 6MOESI state diagram40m
- 7CHI cache line states24m
- 8Cache coherence protocols6m
- 9CHI Protocol fundaments25m
- 10CHI architecture layers48m
- 11Protocol layer - Deep dive33m
- 12Read transaction flow1h 3m
- 13Dataless transactions summary18m
- 14Read transactions1h 35m
- 15Write transactions47m
- 16Write request transaction flow56m
- 17Write Unique full stash19m
- 18CopyBack write transactions26m
- 19Ordering guidelines25m
- 20CHI TRANSFER TYPES - READ DATA SOURCE7m
- 21CHI CHANNELS42m
- 22TRANSACTION STRUCTURE15m
- 23READ TRANSACTIONS1h 5m
- 24DATALESS TRANSACTION8m
- 25DATALESS TRANSACTIONS, CACHE STASHING36m
- 26ORDERING AND COMPACK RULES6m
- 27WriteNoSnpDef19m
- 28CompAck flow11m
- 29Atomic transactions17m
- 30Misc transactions - DVM, PrefetchTgt5m
- 31Transaction retry sequence5m
- 32Snoop transactions14m
- 33Snoop request types21m
- 34Combined Write Requests9m
- 35Transaction identifier fields26m
- 36Address, Control, Data46m
- 37CHI transaction attributes6m
- 38Data transfer1h 15m
- 39Request retry5m
- 40Request types and corresponding snoop requests6m
- 41Interconnect behavior - Snoop requests3m
- 42Response types1h 1m
- 43Misc responses15m
- 44Silent cache state transactions3m
- 45Cache state transitions at requester40m
- 46Cache state transitions at Snoopee28m
- 47Cache state transitions at Snoopee29m
- 48TRANSACTION IDENTIFIER FIELDS23m
- 49ORDERING - MULTICOPY ATOMICITY4m
- 50Channels at different nodes9m
- 51Request channel flit fields35m
- 52Snoop request flit fields16m
- 53Data flit fields, response flit fields17m
- 54flit packet definitions11m
- 55Exclusive accesses27m
- 56Error handling56m
- 57Error response in write transactions23m
- 58Memory tagging extensions55m
- 59Memory tagging extensions summary9m
- 60System control, debug, track and monitoring49m
- 61DVM operations36m
- 62DVM operations summary8m
Your Instructor
S
Sreenivas Reddy
Founder, VLSIGuru
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
What Our Students Say
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
Each session of course is recorded, missed session videos will be s
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts