VLSI Training
Power Aware Design Techniques - VCLP
The Power Aware Design Techniques course, specifically focusing on Voltage and Clock Level Power (VCLP), provides an in-depth understanding of power optimization strategies used in digital design.
- 3 HoursCourse Duration
- 4 SessionsRecorded & Live
- 4.6/5Learner Rating
- 500+Enrolled Learners
Course Overview
The Power Aware Design Techniques course, specifically focusing on Voltage and Clock Level Power (VCLP), provides an in-depth understanding of power optimization strategies used in digital design. The course covers various methods to manage and minimize power consumption at different levels of design, from architectural decisions down to implementation.
Detailed Syllabus
1 modules- Introduction to Low Power
- Need for low power design
- Understanding power intent
- Types of power consumption
- Power reduction techniques
- Special cells for low power techniques
- Power switches
- Isolation cells
- Level shifters
- Always on logic
- Retention registers
- UPF
- UPF commands
- UPF flow
- Power domains
- Power state table
- Retention strategies
- Isolation strategies
- Level shifting strategies
- VCLP tool flow
- Reading the design
- Reading Power intent and running VCLP checks
- VCLP run script
Session-wise Content
4 sessions- 1Need for Low power design, Power reduction techniques
- 2Special cells required for low power techniques
- 3UPF labs ses1 - VCLP
- 4UPF Labs ses2 - VCLP
Your Instructor
S
Sreenivas Reddy
Founder, VLSIGuru
Benefits of eLearning?
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