Demo Videos

• Curriculum

• CXL introduction
  • CXL
  • Flex Bus
• CXL system architecture
  • CXL Type 1, Type 2 and Type 3 devices
  • Multi logical device
  • CXL device scaling
  • CXL fabric
  • G-FAM type3 device
• CXL transaction layer
  • io, CXL.cache, CXL.mem
  • Transaction ordering summary
  • Transaction flows to device attached memory
• CXL Link layers
  • io Link Layer
  • cache and CXL.mem 68B Flit Mode Common Link Layer
  • cachemem Link Layer 256B Flit Mode
• CXL ARB/MUX
  • vLSM states
  • ARB/MUX Link Management Packets
  • Arbitration and Data Multiplexing/Demultiplexing
• Flex Bus Physical Layer
  • Flex Bus.CXL Framing and Packet Layout
  • 256B Flit Mode Retry Buffers
  • Link Training
  • 68B Flit Mode: Recovery.Idle and Config.Idle Transitions to L0
  • L1 Abort Scenario
  • 68B Flit Mode: Exit from Recovery
  • Retimers and Low Latency Mode
• Switching
  • Switch configuration and composition
  • io, CXL.cachemem Decode and Forwarding
  • CXL Switch PM
  • CXL Switch RAS
  • Fabric Manager Application Programming Interface
  • CXL fabric architecture
• Control and status registers
  • Configuration space registers
  • Memory mapped registers
• Reset, Initialization, configuration and manageability
  • CXL Boot and Reset Overview
  • CXL Device Boot Flow
  • CXL System Reset Entry Flow
  • CXL Device Sleep State Entry Flow
  • Function Level Reset (FLR)
  • Cache Management
  • CXL Reset, Hot-Plug
  • Software Enumeration
  • RCD Enumeration
• Power management
  • CXL power management
  • io Link power management
• CXL security
  • CXL IDE overview
  • io IDE
  • cachemem IDE
• Reliability, Availability and Serviceability
  • CXL error handling
  • CXL error injection
  • CXL viral handling
• Performance considerations
  • Performance monitoring

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