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CXL Training

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CXL Training

About Course

CXL training is a 67 hours training covering all the aspects starting from CXL system architecture, transaction layer, link layer, arbitration, multiplexing, flex bus physical layer,
switching, register and reset, initialization, configuration, etc.

Course also focus on power management, security, performance, etc.

Demo Videos

Unit Number	Topic	Duration (Mins)
1	CXL DEMO SES	197
2	Training schedule, Pre-requisites	14
3	CXL SES1	85
4	CXL Overview	15
5	CXL SES2	75
6	Need for CXL	67
7	CXL SES2 PART 1	78
8	CXL specific questions	13
9	CXL SES2 PART 2	60
10	CXL course basics	47
11	CXL SES2 PART 3	52
12	Cache coherent interconnect	42
13	CXL SES 3	91
14	MOESI state diagram	85
15	CXL SES4 PART 1	84
16	CXL features	38
17	CXL protocol types	36
18	CXL SES4 PART 2	74
19	Questions	10
20	CXL SES5 PART 1	77
21	MESI protocol	47
22	CXL SES5 PART 2	64
23	CXL multi protocol support with assymetry	22
24	CXL SES6 PART 1	68
25	Two coherency biases	6
26	CXL SES6 PART 2	55
27	CXL SES7	94
28	CXL - different layers	9
29	CXL SES8 PART 1	77
30	CXL.io transaction layers	44
31	CXL SES8 PART 2	85
32	CXL.cache	52
33	CXL.cache	31
34	CXL SES9 PART 1	78
35	CXL doubts	9
36	CXL SES9 PART 2	62
37	H2D request, H2D response, H2D Data	27
38	SES10_CXL_P1_256B_Flit_Packing_rules	19
39	CXL.cache transaction descriptor	22
40	SES10_CXL_P2_256B_Flit_Credit_Return	18
41	SES10_CXL_P3_CXL_Control_messages_256B_flit_mode	10
42	CXL.Cache WrInv transaction, CXL.cache Device to host requests	84
43	CXL.cache D2H Response, request and response mapping	72
44	SES10_CXL_P4_Link_layer_initialization_256B_flit_mode	4
45	SES10_CXL_P5_ARB_MUX	9
46	Host to device responses	32
47	SES10_CXL_P6_ARB_MUX_vLSM_states	10
48	System capability enabled by CXL	7
49	SES11 CXL PART 1	58
50	CXL.mem	38
51	M2S req transactions, M2S RwD	24
52	SES11 CXL PART 2	46
53	M2S Back invalidate snoop	12
54	SES12 CXL PART 1	73
55	SES12 CXL PART 2	31
56	S2M No data response	28
57	SES13 CXL	71
58	Transacton flows to device attached memory	67
59	SES13 CXL PART 2	48
60	Block back invalidation snoops	25
61	SES14 CXL	71
62	Link layer overview	31
63	SES15 CXL	72
64	Link layer features, flit format for H2D and M2S transactions	94
65	D2H and S2M transaction flit format, Data transfer with Multi data header	77
66	Link layer control flit	39
67	Link layer initialization	44
68	LLCRD forcing, LLR control flits	27
69	LLR state machines	52
70	Link layer 256B flit mode, flit packing rules	62
71	256B Flit Packing rules	19
72	256B Flit Credit Return	18
73	CXL Control messages 256B flit mode	10
74	Link layer initialization 256B flit mode	4
75	CXL ARB MUX	9
76	ARB MUX vLSM states	10
77	CXL ARBMUX vLSM state transactions	58
78	State request ALMP	46
79	FlexBus physical layer	26
80	68B Flit mode	36
81	framing errors	11
82	256B flit mode	31
83	Link training	71
84	256B flit mode negotiation	5
85	IO throttling, Link width degradation and speed downgrade	42
86	Switching	18
87	Configuration and status registers	42
88	reset, initialization, configuration and managebility	11
89	CXL verification, test plan development, testbench architecture diagram	72

Curriculum

CXL introduction
- CXL
- Flex Bus
CXL system architecture
- CXL Type 1, Type 2 and Type 3 devices
- Multi logical device
- CXL device scaling
- CXL fabric
- G-FAM type3 device
CXL transaction layer
- io, CXL.cache, CXL.mem
- Transaction ordering summary
- Transaction flows to device attached memory
CXL Link layers
- io Link Layer
- cache and CXL.mem 68B Flit Mode Common Link Layer
- cachemem Link Layer 256B Flit Mode
CXL ARB/MUX
- vLSM states
- ARB/MUX Link Management Packets
- Arbitration and Data Multiplexing/Demultiplexing
Flex Bus Physical Layer
- Flex Bus.CXL Framing and Packet Layout
- 256B Flit Mode Retry Buffers
- Link Training
- 68B Flit Mode: Recovery.Idle and Config.Idle Transitions to L0
- L1 Abort Scenario
- 68B Flit Mode: Exit from Recovery
- Retimers and Low Latency Mode
Switching
- Switch configuration and composition
- io, CXL.cachemem Decode and Forwarding
- CXL Switch PM
- CXL Switch RAS
- Fabric Manager Application Programming Interface
- CXL fabric architecture
Control and status registers
- Configuration space registers
- Memory mapped registers
Reset, Initialization, configuration and manageability
- CXL Boot and Reset Overview
- CXL Device Boot Flow
- CXL System Reset Entry Flow
- CXL Device Sleep State Entry Flow
- Function Level Reset (FLR)
- Cache Management
- CXL Reset, Hot-Plug
- Software Enumeration
- RCD Enumeration
Power management
- CXL power management
- io Link power management
CXL security
- CXL IDE overview
- io IDE
- cachemem IDE
Reliability, Availability and Serviceability
- CXL error handling
- CXL error injection
- CXL viral handling
Performance considerations
- Performance monitoring

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Course Instructor

Dedicated Trainer Accessible On Phone / Email / Whatsapp
Trainer Exp: 15 Years

Price - ₹9,000 + GST

₹11,700 (30% Off)

10 hours left to avail at this price

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