FPGA System Design Training
FPGA System Design Training is a comprehensive e-learning program designed to provide in-depth exposure to the complete FPGA design and implementation flow.
- 40 HoursCourse Duration
- 25 SessionsRecorded & Live
- 4.6/5Learner Rating
- 4000+Enrolled Learners
Course Overview
FPGA System Design Training – Course Overview
About the Course
FPGA System Design Training is a comprehensive e-learning program designed to provide in-depth exposure to the complete FPGA design and implementation flow. The course focuses on FPGA-based system development starting from RTL coding and progressing through prototyping, implementation, and hardware validation. It enables learners to understand how digital designs are mapped onto FPGA hardware and verified in real-time environments.
This training provides detailed knowledge of FPGA architecture, internal resources, and I/O structures. Learners gain practical understanding of timing closure, design constraints, and optimization techniques required to meet performance goals on FPGA platforms. The course also covers FPGA implementation using both RTL-based design flow and IP-based design methodologies commonly adopted in industry projects.
In addition to hardware design, the course introduces FPGA debugging techniques and software integration concepts. Participants gain exposure to software development kit (SDK) environments and learn how to boot and run FPGA-based systems using Petalinux or Ubuntu. This program is suitable for electronics engineers, embedded system developers, and VLSI professionals seeking expertise in FPGA system design and prototyping.
Course Objectives
The primary objectives of this course are to:
• Build strong understanding of FPGA architecture and internal resources
• Learn RTL-based FPGA design and implementation flow
• Understand FPGA timing closure and constraint development
• Implement FPGA designs using both RTL mode and IP-based mode
• Apply FPGA debugging and validation techniques on hardware
• Gain exposure to software development kit (SDK) environments
• Learn system booting using Petalinux and Ubuntu on FPGA platforms
• Prepare learners for FPGA design and embedded system roles
Detailed Syllabus
16 modules- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
- Digital Design basics
- combinational logic
- sequential logic, FF, latch, counters
- Memories
- Refer to Advanced digital design training page for detailed course contents
- www.vlsiguru.com/digital-design-complete
- Shells
- File and directory management
- User administration
- Environment variables
- Commonly used commands
- Shell scripting basics
- SEd and AWK
- Revision management
- Makefiles
- SOC Architecture overview
- SOC design concepts
- SOC verification concepts
- SOC Components
- SOC use cases
- SOC Testbench architecture
- SOC Test Case coding
- SOC verification differences with module verification
- Verilog language constructs
- Verilog design coding examples covering more than 20 standard designs
- www.vlsiguru.com/verilog-training/
- PAL, CPLD and FPGA basics
- FPGA Design Flow
- Internals of FPGA and CPLD
- Logic implementation
- FPGA Architectures of various FPGA vendors
- Anti-fuse and SRAMS
- Logic elements and Look-up Tables
- Dedicated multipliers
- Distributed RAM
- Shift registers
- MMCM
- Kintex
- Zynq
- Virtex Architectures
- Introduction and usage of IP cores·
- Modelsim/Icarus Verilog simulation
- Design Synthesis
- Design constraining and pin locking
- Timing analysis
- slack calculation
- Data loss due to large skew
- Maximum skew calculations with examples
- Period constraints
- Area and Power Constraints
- Static Timing Analysis
- FPGA programming
- Translate
- Map
- Floor plan
- Place and Route
- Post map and Post P&R simulation
- XDC constraints
- Reading and analysing reports-post synthesis
- Post map simulation
- Post P·&R simulation
- Configuring FPGAs
- FSM Extraction
- Timing Simulation using Modelsim/Icarusverilog
- Programming using JTAG
- Debugging techniques
- Debugging using chip scope and Logic analyzers
- Protocols on FPGA
- High Speed SERDES
- Identification of the issues/resolving
- FPGA SDK environment
- FPGA Device selection
- PERL Interpreter
- Variables
- File management
- Subroutines
- Regular expressions
- Object oriented PERL
- PERL modules
- Facing interviews effectively
- industry work culture
- Group discussions
Session-wise Content
25 sessions · 39h 56m- 1FPGA DEMO SES11h
- 2FPGA SES22h 32m
- 3FPGA SES32h 30m
- 4FPGA SES42h 32m
- 5FPGA SES552m
- 6FPGA SES62h 15m
- 7FPGA SES71h 5m
- 8FPGA SES81h 6m
- 9FPGA SES92h 6m
- 10FPGA SES101h 23m
- 11FPGA SES111h 36m
- 12FPGA SES122h 12m
- 13FPGA SES131h 34m
- 14FPGA SES141h 7m
- 15FPGA SES151h 8m
- 16FPGA SES161h
- 17FPGA SES172h 32m
- 18FPGA SES182h 19m
- 19FPGA SES1952m
- 20FPGA SES2045m
- 21FPGA SES211h 8m
- 22FPGA SES2222m
- 23FPGA SES232h
- 24FPGA SES242h 56m
- 25FPGA SES251h 4m
Your Instructor
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
What Our Students Say
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Each aspect of course is supported by a lot of hands on exercises and lab.
- FPGA timing as well as prototyping.
- FPGA validation and debugging.
- Dedicated lab sessions with the tool as well as the hardware boards.
- Expertise to C programming
- Exposure to Digital design basics
Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Student can continue to work from institute till he/she gets job
- Student has option to repeat the course as required
- Option to meet trainer in person to clarify doubts