PCIe Data link Layer UVC Development Training
PCIe Data link layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and DLL-TL interface.
- 24 HoursCourse Duration
- 26 SessionsRecorded & Live
- 4.6/5Learner Rating
- 500+Enrolled Learners
Course Overview
About Course
PCIe Data link layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and DLL-TL interface. These UVC are integrated with DLL RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding. Sessions also focused on developing the sequences for AXI, TL-DLL and DLL-PL interfaces, using these sequences to create the testcases. Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.
Detailed Syllabus
2 modules- Introduction
- Protocol overview
- Features
- Scenarios
- Verification plan
- Data link layer RTL coding
- DLL Testbench architecture, testplan development
- UVC architecture and components
- UVC component coding
- AXI UVC, DLL-TL and DLL-PL UVC
- Testbench component integration
- UVC sequence coding for AXI and DLL interface
- Testcase coding
- Testcase run and waveform analysis
- Testbench integration
- Simulations and waveform analysis
- Functional coverage analysis
Session-wise Content
26 sessions · 23h 20m- 1PCIe DLL course overview, features, course pre-requisites29m
- 2DLL architecture39m
- 3DLL design interfaces11m
- 4Question: DLL buffer size1m
- 5DLL design FSM and states16m
- 6DLL RTL coding43m
- 7PCIe DLL TB bringup57m
- 8DLL TB development from scratch1h 18m
- 9Physical layer sequence library coding1h 9m
- 10Driver coding and DLL.SV design files updates1h 17m
- 11tl_item update11m
- 12dll.sv and driver update for processing the TLP1h 28m
- 13TLP to link packet conversion, store LP to buffer1h 21m
- 14Fetching link packet from buffer and driving link packet to Physical layer1h 30m
- 15Physical layer agent collecting link packet, PL sequence library update to drive completion TLP54m
- 16Memory write followed by memory read TLP1h 25m
- 17PL driver generate completion TLP in response to Memory read TLP59m
- 18PL and TL agent monitor and coverage coding1h 13m
- 19DLL scoreboard coding and test case passing47m
- 20DLL TB coverage report generation23m
- 21DLL TB sequence development1h 2m
- 22DLL features to implement in TB21m
- 23DLL compile clean up45m
- 24DLL simulation bring up55m
- 25DLL VC0 flow control bring up2h
- 26DLL flow control test case bring up1h 6m
Your Instructor
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What Our Students Say
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
- Each session of course is recorded, missed session videos will be s
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts