PCIe Physical Layer UVC Development Training
PCIe Physical layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and PL-PHY interface.These UVC are integrated with Physical Layer RTL code to develop the complete testbench.
- 28 HoursCourse Duration
- 30 SessionsRecorded & Live
- 4.7/5Learner Rating
- 120+Enrolled Learners
Course Overview
About Course
PCIe Physical layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and PL-PHY interface.
These UVC are integrated with Physical Layer RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding.
Sessions also focused on developing the sequences for AXI, TL-DLL and PL-PHY interfaces, using these sequences to create the testcases.
Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.
Detailed Syllabus
2 modules- Introduction
- Protocol overview
- Features
- Scenarios
- Verification plan
- Physical layer RTL coding
- Physical layer Testbench architecture, testplan development
- UVC architecture and components
- UVC component coding
- AXI UVC, DLL-TL and PL-PHY UVC
- Testbench component integration
- UVC sequence coding for AXI, TL and PHY interface
- Testcase coding
- Testcase run and waveform analysis
- Testbench integration
- Simulations and waveform analysis
- Functional coverage analysis
Session-wise Content
30 sessions · 27h 38m- 1PL TB Physical layer overview, PL interface, RTL and TB template coding1h 14m
- 2PL test bench template coding49m
- 3PL LTSSM Detect to Polling.35m
- 4PL Generate TS1 for Polling transitions24m
- 5Polling.Active TS1 transmit1h 5m
- 6Polling.Active TS1 TS2 handshake till Configuration state46m
- 7Link training update from Single lane to multi lane link29m
- 8Configuration.LinkWidth.Start to accept State57m
- 9CONFIG.LINKWIDTH_ACCEPT to CONFIG.LANENUM_ACCEPT1h
- 10CONFIG.LANENUM_ACCEPT to L01h 42m
- 11DLL Agent FC_INIT Sequence coding55m
- 12PL DLL transmit path specific State machine coding59m
- 13DLLP framing and transmit on DLL-PL interface38m
- 14DLLP transmit per lane54m
- 15DLLP transmit issue fix36m
- 16PIPE UVC receiving DLLPs30m
- 17FC DLLP driven by PIPE UVC in response to Design DLLPs1h
- 18PL Design collecting DLLP properly58m
- 19DLL RX UVC Collecting DLLPs1h 4m
- 20DLL TX UVC Generating TLPs1h 12m
- 21PL DUT Collecting TLPs, framing and sending to PIPE UVC1h 2m
- 22PIPE UVC Collecting TLPs and analyzing TLP header fields1h 3m
- 23PIPE UVC transmitting CplD TLP and DUT Collecting59m
- 24DLL UVC collecting CplD TLP from PL DUT53m
- 25PL DUT going to Recovery51m
- 26Recovery sub state transitions and then to L045m
- 27DLL Transmit interface monitor coding43m
- 28DLL RX monitor, PIPE TX interface monitor and coverage coding1h 36m
- 29Scoreboard coding22m
- 30Scoreboard mismatch debug1h 37m
Your Instructor
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
What Our Students Say
I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.
The admins are very much co-operative and understandable and help you throughout the course.
The concepts taught are in a very simplified manner and every lecture is recorded.
Very much satisfied will recommend to any VLSI enthusiast
VLSIGURU is a best place to get complete knowledge on VLSI domain. It has excellent lab facility which helps to gain practical knowledge. It is a place where a trainee can develop technical as well as communication skills which makes a person job ready. Trainers are co-operative and helpful in explaining the course. Over all it is the best institute for VLSI training not only for experienced but also for the freshers.
I completed course in the institute and I would say VLSIGURU is the best institute at Bangalore. They have taught each concepts of in details and every faculty member is extremely supportive, whenever I had doubts they had it cleared for me which I liked the most. Also LAB classes are very good, they give tool access and you can explore on the tools like an adventurer. One of the greatest boon VLSIGURU has is they keep the live sessions recorded so that if anyone need to revisit the concepts again they can re-watch it.
Faculties are well experienced and very helpful.
I joined the online weekend classes but all my doubts and concepts were cleared by faculty members.
They even provide extra time if needed to assist you.
Frequently Asked Questions
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
- Each session of course is recorded, missed session videos will be s
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts