PCIe Transaction Layer UVC Development Training

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PCIe Transaction Layer UVC Development Training

About Course

PCIe Transaction layer UVC development is focused on developing UVC components for PCIe AXI and TL-DLL interface. These UVC are integrated with TL RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding. Sessions also focused on developing the sequences for AXI and TL-DLL interfaces, using these sequences to create the testcases. Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.

Demo Videos
Unit NumberTopicDuration (Mins)
1Listing down features, Top level and micro architecture, Interfaces, Design FSM - states, Basic RTL coding including FSM69
2UVM TB template development, Develop sequences for register programming through AXI interface106
3Linkup indication, TL and DLL sequence item coding, VC initialization, Generate CFG WR/RD TLP87
4Frame CFG TLP, Drive the TLP76
5Update DLL responder for enumeration, process the CmplD TLP from DLL responder93
6Analyze the waveform, Fix issue with CFG RD header94
7Read BAR, Configure BAR registers88
8Memory Write TLP implementation, TL DMA coding for fetching Memory write TLP payload85
9Frame memory write TLP, Drive TLP on TL-DLL interface30
10Storing Completion TLP data to memory40
11AXI writes to memory40
12Config Wr1/Rd1, Multiple MWr and MRd TLPs81
13AXI processor interface & DLL-RX interface monitor and AXI coverage coding61
14DLL-RX interface monitor issue fixing for one missing data31
15DLL-TX interface monitor implementation, collect the transmit TLPs21
16AXI monitor implementation for collecting transactions at memory interface16
17Memory interface AXI monitor issue fix, DLL-RX interface Covergroup coding45
18TL RTL Fixing for Packet driving issues70
19TL scoreboard coding, test passing60

 

Curriculum

Introduction
Protocol overview
Features
Scenarios
Verification plan
Transaction layer RTL coding
TL Testbench architecture, testplan development
UVC architecture and components
UVC component coding
AXI UVC, TL-DLL UVC
Testbench component integration
UVC sequence coding for AXI and DLL interface
Testcase coding
Testcase run and waveform analysis
Testbench integration
Simulations and waveform analysis
Functional coverage analysis

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  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹7,500 + GST

₹10,000    (25% Off)

10 hours left to avail at this price

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