VLSI Training
Physical design Interview preparation
· Covering 1200+ questions on Physical design, Synthesis, STAo Mostly real time design related questions are covered· Questions based on CMOS, Layout and Fabrication· Questions Based on Different…
- 57 HoursCourse Duration
- 179 SessionsRecorded & Live
- 4.6/5Learner Rating
- 500+Enrolled Learners
Course Overview
- Course content
- · Covering 1200+ questions on Physical design, Synthesis, STA
- o Mostly real time design related questions are covered
- · Questions based on CMOS, Layout and Fabrication
- · Questions Based on Different inputs during each step of
- Physical design and sanity checks
- · Questions based on Static timing Analysis.
- · Questions based on Fixing issues after each physical design
- · Lower Technology issues and fixing
- · Signal integrity issues and fixes
- · Analysis of timing reports and QoR reports after each stage of physical design using TCL and UNIX .
- · Questions related to Synthesis, UPF and SDC
- · IR Drop and Electromigration questions
Detailed Syllabus
1 modules- Interview preparation
- .vimrc
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
Session-wise Content
179 sessions · 56h 19m- 1synthesis and its files12m
- 2.db file discussion34m
- 3.mw and .ndm file discussion8m
- 4.lef file discussion7m
- 5flow of synthesis16m
- 6difference between compile and compile_ultra steps involved in compile ultra16m
- 7scan-chain discussion9m
- 8outputs for synthesis9m
- 9App_var to load logical lib5m
- 10Discussion on timing analysis and its optimization in synthesis5m
- 11DRVs optimization and synthesis flow performed in the tool7m
- 12lib updation required9m
- 13Discussion on gate level netlist19m
- 14violations and fixes example27m
- 15Discussion on checks after synthesis28m
- 16Models for RC extraction9m
- 17Discussion on SDC files contents of sdc18m
- 18Discussion on types of clocks7m
- 19Discussion on delays and timing paths37m
- 20Discussion on timing exceptions11m
- 21Questions on thinking20m
- 22Discussion on constraints4m
- 23Calculation of input and output delay8m
- 24Main purpose of virtual clock7m
- 25Discussion on Floorplan core and die area creation15m
- 26port_placement macro_placement discussion18m
- 27physical only cells sanity checks discussion13m
- 28keepout placement blockages20m
- 29Bounds guides discussion16m
- 30spare cells8m
- 31Questions-Discussion (a) sanity_checks and utilization9m
- 32Questions-Discussion (b) core and die area29m
- 33Questions-Discussion (c) ESD and macros17m
- 34Basic cmos & input files .lib8m
- 35Basic cmos & input files .upf and other input files38m
- 36initialize floorplan22m
- 37powerplan18m
- 38checks in powerplan lab17m
- 39Question discussion - power analysis18m
- 40Question discussion - upf & power reduction techniques25m
- 41Question discussion - different flavour & types of cells11m
- 42Some realtime challenges faced6m
- 43power_plan flow18m
- 44power_planning at full chip level and block level20m
- 45power_rings12m
- 46How different height cells getting power and IR drop12m
- 47EM violations & hotspots18m
- 48Fixing of rails and macro pin violations10m
- 49Sta concepts37m
- 50Why hold is given more importance after cts17m
- 51HVT, RVT and LVT cells32m
- 52virtual and generated clock23m
- 53Max tran and max cap & pvt condition36m
- 54Modes, Corners and Scenarios12m
- 55Timing Exceptions - different cycle paths17m
- 56PBA & GBA mode14m
- 57DRVs {max_tran, max_cap, max_fanout}29m
- 58path grouping17m
- 59fix for setup and hold at each stage33m
- 60Derate17m
- 61STARRC extraction crpr25m
- 62Prime Time Inputs5m
- 63Crosstalk Noise26m
- 64crosstalk delay11m
- 65How to reduce crosstalk12m
- 66Crpr in crosstalk8m
- 67Useful skew methods6m
- 68Time borrowing13m
- 69CCD flow10m
- 70How RC value is calculated4m
- 71ECO flow for the timing19m
- 72Physical and logical aware eco & bottleneck cell9m
- 73Some Summarised questions26m
- 74Placement_blockage15m
- 75keepout margin and congestion18m
- 76Path grouping and Bounds18m
- 77placement18m
- 78tool aspect place_opt13m
- 79banking & debanking15m
- 80Questionaire & legalization4m
- 81coarse_placement & zic timing16m
- 82different app options used for placement11m
- 83cell-density10m
- 84pin-density19m
- 85routing-congestion22m
- 86HFNS6m
- 87Load splitting & clonning & DRVs10m
- 88global virtual routing & magnet placement7m
- 89bound & multibit banking, upsizing and inserting buffer command6m
- 90setup fixes after placement4m
- 91path grouping5m
- 92sanity checks after placement2m
- 93saif file7m
- 94timing driven placement1m
- 95What is CTS9m
- 96Inputs for CTS17m
- 97How tool perform CTS22m
- 98Why there is a need of more routing resources in 1 metal layer5m
- 99CTS.tcl24m
- 100Checks before CTS21m
- 101report clock qor12m
- 102Why clock nets are given more priority6m
- 103Skew group, ndr, clk buffers14m
- 104Miscellaneous questions on cts26m
- 105slew & shielding4m
- 106why we solve setup before cts and hold after cts4m
- 107NDR & uncertainity20m
- 108which design is more complicated10m
- 109clock tweaking & clock gating14m
- 110Difference between HFNS and CTS5m
- 111checks ,fixes and reports after cts14m
- 112pulse-width vio15m
- 113clock gating vio3m
- 114setup & hold7m
- 115multipoint cts7m
- 116Crprcppr3m
- 117doubt discussion27m
- 118routing15m
- 119Inputs for routing9m
- 120pre-routing checks24m
- 121physical verification7m
- 122Inputs for PV and violations15m
- 123DRC14m
- 124Antenna effect12m
- 125double patterning16m
- 126routing practical9m
- 127global routing & pitch7m
- 128search & repair and routing blockage5m
- 129checks after routing12m
- 130buffer on route14m
- 131import design17m
- 132floorplan and port placement1h 9m
- 133macro placement53m
- 134powerplanning26m
- 135placement2h 13m
- 136cts42m
- 137IR drop13m
- 138Types of power dissipation19m
- 139Role of Redhawk team14m
- 140Ses 15 P 4 Input files required for Redhawk checks8m
- 141APL & ATL - (Appache power library) & (Appache Tech Library)30m
- 142CMM model11m
- 143fsdbvcd file10m
- 144timing window file16m
- 145true time non true time fsdb10m
- 146Inputs for redhawk30m
- 147time_window SDF {Standard delay format}14m
- 148Different types of analysis26m
- 149Dynamic vectorless analysis16m
- 150Dynamic vectored analysis19m
- 151What results are analyzed after each analysis17m
- 152What are fixing method for more IR drop12m
- 153LVS checks on clock pins after cts52m
- 154Skew group based question11m
- 155when to insert level shifters17m
- 156whether all clock pins has clock gating cells or not50m
- 157applying keepout margin around the cell29m
- 158Doubt Questions26m
- 159How to report nets having drc violations1h
- 160Script writting to get the ff which is not having clock gating cells46m
- 161Miscellaneous Questions discussion32m
- 162Antenna diode13m
- 163Insert buffer near a pin48m
- 164Doubts14m
- 165antenna violation11m
- 166How to insert buffer29m
- 167Antenna diode insertion44m
- 168Why DRC is checked in a seperate tool again21m
- 169Why we cant do base level drc check in icc2 or innovus4m
- 170Input files required for PV8m
- 171How to generate final merged GDS18m
- 172What are different DRC checks23m
- 173LVS19m
- 174Outputs of LVS11m
- 175ERC8m
- 176Double patterning Rule check15m
- 177ADDITIONAL MISCELLANEOUS QUESTIONS1h 43m
- 178ADDITIONAL MISCELLANEOUS QUESTIONS - 21h 47m
- 179ADDITIONAL MISCELLANEOUS QUESTION SES3 29DEC20231h 32m
Your Instructor
S
Sreenivas Reddy
Founder, VLSIGuru
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