Physical design Interview preparation

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Physical design Interview preparation

Course content
· Covering 1200+ questions on Physical design, Synthesis, STA
o Mostly real time design related questions are covered
· Questions based on CMOS, Layout and Fabrication
· Questions Based on Different inputs during each step of
Physical design and sanity checks
· Questions based on Static timing Analysis.
· Questions based on Fixing issues after each physical design
· Lower Technology issues and fixing
· Signal integrity issues and fixes
· Analysis of timing reports and QoR reports after each stage of physical design using TCL and UNIX .
· Questions related to Synthesis, UPF and SDC
· IR Drop and Electromigration questions

Unit Number	Topic	Duration (Mins)
1	synthesis and its files	12
2	.db file discussion	34
3	.mw and .ndm file discussion	8
4	.lef file discussion	7
5	flow of synthesis	16
6	difference between compile and compile_ultra steps involved in compile ultra	16
7	scan-chain discussion	9
8	outputs for synthesis	9
9	App_var to load logical lib	5
10	Discussion on timing analysis and its optimization in synthesis	5
11	DRVs optimization and synthesis flow performed in the tool	7
12	lib updation required	9
13	Discussion on gate level netlist	19
14	violations and fixes example	27
15	Discussion on checks after synthesis	28
16	Models for RC extraction	9
17	Discussion on SDC files contents of sdc	18
18	Discussion on types of clocks	7
19	Discussion on delays and timing paths	37
20	Discussion on timing exceptions	11
21	Questions on thinking	20
22	Discussion on constraints	4
23	Calculation of input and output delay	8
24	Main purpose of virtual clock	7
25	Discussion on Floorplan core and die area creation	15
26	port_placement macro_placement discussion	18
27	physical only cells sanity checks discussion	13
28	keepout placement blockages	20
29	Bounds guides discussion	16
30	spare cells	8
31	Questions-Discussion (a) sanity_checks and utilization	9
32	Questions-Discussion (b) core and die area	29
33	Questions-Discussion (c) ESD and macros	17
34	Basic cmos & input files .lib	8
35	Basic cmos & input files .upf and other input files	38
36	initialize floorplan	22
37	powerplan	18
38	checks in powerplan lab	17
39	Question discussion - power analysis	18
40	Question discussion - upf & power reduction techniques	25
41	Question discussion - different flavour & types of cells	11
42	Some realtime challenges faced	6
43	power_plan flow	18
44	power_planning at full chip level and block level	20
45	power_rings	12
46	How different height cells getting power and IR drop	12
47	EM violations & hotspots	18
48	Fixing of rails and macro pin violations	10
49	Sta concepts	37
50	Why hold is given more importance after cts	17
51	HVT, RVT and LVT cells	32
52	virtual and generated clock	23
53	Max tran and max cap & pvt condition	36
54	Modes, Corners and Scenarios	12
55	Timing Exceptions - different cycle paths	17
56	PBA & GBA mode	14
57	DRVs {max_tran, max_cap, max_fanout}	29
58	path grouping	17
59	fix for setup and hold at each stage	33
60	Derate	17
61	STARRC extraction crpr	25
62	Prime Time Inputs	5
63	Crosstalk Noise	26
64	crosstalk delay	11
65	How to reduce crosstalk	12
66	Crpr in crosstalk	8
67	Useful skew methods	6
68	Time borrowing	13
69	CCD flow	10
70	How RC value is calculated	4
71	ECO flow for the timing	19
72	Physical and logical aware eco & bottleneck cell	9
73	Some Summarised questions	26
74	Placement_blockage	15
75	keepout margin and congestion	18
76	Path grouping and Bounds	18
77	placement	18
78	tool aspect place_opt	13
79	banking & debanking	15
80	Questionaire & legalization	4
81	coarse_placement & zic timing	16
82	different app options used for placement	11
83	cell-density	10
84	pin-density	19
85	routing-congestion	22
86	HFNS	6
87	Load splitting & clonning & DRVs	10
88	global virtual routing & magnet placement	7
89	bound & multibit banking, upsizing and inserting buffer command	6
90	setup fixes after placement	4
91	path grouping	5
92	sanity checks after placement	2
93	saif file	7
94	timing driven placement	1
95	What is CTS	9
96	Inputs for CTS	17
97	How tool perform CTS	22
98	Why there is a need of more routing resources in 1 metal layer	5
99	CTS.tcl	24
100	Checks before CTS	21
101	report clock qor	12
102	Why clock nets are given more priority	6
103	Skew group, ndr, clk buffers	14
104	Miscellaneous questions on cts	26
105	slew & shielding	4
106	why we solve setup before cts and hold after cts	4
107	NDR & uncertainity	20
108	which design is more complicated	10
109	clock tweaking & clock gating	14
110	Difference between HFNS and CTS	5
111	checks ,fixes and reports after cts	14
112	pulse-width vio	15
113	clock gating vio	3
114	setup & hold	7
115	multipoint cts	7
116	Crprcppr	3
117	doubt discussion	27
118	routing	15
119	Inputs for routing	9
120	pre-routing checks	24
121	physical verification	7
122	Inputs for PV and violations	15
123	DRC	14
124	Antenna effect	12
125	double patterning	16
126	routing practical	9
127	global routing & pitch	7
128	search & repair and routing blockage	5
129	checks after routing	12
130	buffer on route	14
131	import design	17
132	floorplan and port placement	69
133	macro placement	53
134	powerplanning	26
135	placement	133
136	cts	42
137	IR drop	13
138	Types of power dissipation	19
139	Role of Redhawk team	14
140	Ses 15 P 4 Input files required for Redhawk checks	8
141	APL & ATL - (Appache power library) & (Appache Tech Library)	30
142	CMM model	11
143	fsdbvcd file	10
144	timing window file	16
145	true time non true time fsdb	10
146	Inputs for redhawk	30
147	time_window SDF {Standard delay format}	14
148	Different types of analysis	26
149	Dynamic vectorless analysis	16
150	Dynamic vectored analysis	19
151	What results are analyzed after each analysis	17
152	What are fixing method for more IR drop	12
153	LVS checks on clock pins after cts	52
154	Skew group based question	11
155	when to insert level shifters	17
156	whether all clock pins has clock gating cells or not	50
157	applying keepout margin around the cell	29
158	Doubt Questions	26
159	How to report nets having drc violations	60
160	Script writting to get the ff which is not having clock gating cells	46
161	Miscellaneous Questions discussion	32
162	Antenna diode	13
163	Insert buffer near a pin	48
164	Doubts	14
165	antenna violation	11
166	How to insert buffer	29
167	Antenna diode insertion	44
168	Why DRC is checked in a seperate tool again	21
169	Why we cant do base level drc check in icc2 or innovus	4
170	Input files required for PV	8
171	How to generate final merged GDS	18
172	What are different DRC checks	23
173	LVS	19
174	Outputs of LVS	11
175	ERC	8
176	Double patterning Rule check	15
177	ADDITIONAL MISCELLANEOUS QUESTIONS	103
178	ADDITIONAL MISCELLANEOUS QUESTIONS - 2	107
179	ADDITIONAL MISCELLANEOUS QUESTION SES3 29DEC2023	92

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