Physical Design Training with hands on ICC2 projects
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Physical Design Training with hands on ICC2 projects
- Course Duration: 184 Hours
- 4.6 Star (Rating)
- 5000+ (Student Enrolled till Now)
About Course
Physical Design Training is a 4 months course (+1.5 months for freshers covering Device fundamentals, IC fabrication, timing concepts. advanced digital design, analog design basics, and UNIX OS) structured to enable aspiring engineers get in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, Placement, power planning, scan chain reordering, global routing, clock tree synthesis, power analysis and ECO. Course also involves multiple hands on projects using Synopsys Implementation flow(DC, ICC II, Star RC, PT, ICV). It is among widely used PnR flow in industry.
Physical Design training program is well illustrated and supported with real-time examples from the industry. Floorplanning, Placement and Routing, Clock Tree Synthesis, Final Routing and Timing Closure forms the core of the Physical Design Training program structure. Thorough and micro level wide understanding of the concepts across all the Physical Design flow would be the key highlight of this program. Complete Theory Sessions and complementing Lab Sessions with projects (Block level and Full chip level) from Netlist to GDSII, guided well by expert trainer are offered for every candidate of this Physical Design Training program.
Physical Design Training is supported using 15+ assignments covering all aspects physical design implementation flow including practical aspects. Assignments are detailed and well structured to cover all the aspects of Physical Design. These assignments will solved as part of course lectures. Student will have 4 months access to tool from date of course registration.
VLSIGuru Institute is setup in 2012, helped 1000+ students find right career opportunities. VLSIGuru offers affordable Physical Design Training in Bangalore and Noida. Course will Online Physical Design Training is offered for students based out of Bangalore.
Below are the Physical design Training topics.
Netlist to GDSII flow :
Initial Design Setup
Importing design
Floorplanning
Power Planning
Placement
Scan chain re-ordering and re-partitioning
Global Routing
Clock Tree Synthesis
Detailed Routing
Power Analysis (static and dynamic)
Engineering Change Order flow (ECO)
Design For Manufacturability
Demo Videos
| Unit Number | Topic | Duration (Mins) |
| 1 | Introduction to digital system | 25 |
| 2 | Number system introduction and Radix conversion | 61 |
| 3 | Compliments of the number systems and 1 s and 2 s Compliments | 93 |
| 4 | 9 s and 10 s Compliments, 7 s and 8 s Compliments and 15 s and 16 s Compliments | 65 |
| 5 | Gates and its truth table and Why NAND is preferred over NOR gate | 72 |
| 6 | NAND and NOR Realization | 67 |
| 7 | SOP and POS form, minterm, Maxterm canonical SOP and POS form | 56 |
| 8 | Boolean equations Switching equations | 26 |
| 9 | Boolean minimization techniques and K -map(2-variables,3-variables,4-variables) and Logisim tool introduction | 100 |
| 10 | Implicants, PI, EPT, NEPT and RPI | 55 |
| 11 | K -map(5-variables,6-variables) | 26 |
| 12 | K -map with don t care functions | 27 |
| 13 | Building of combinational logic circuits (code converters) | 50 |
| 14 | Code converters continues | 43 |
| 15 | Arithmetic circuits (HA, FA and Parallel Adder) | 64 |
| 16 | Subtractors using compliments (HS, FS) | 62 |
| 17 | MSI circuits (Multiplexers) and Gates using Muxs | 67 |
| 18 | Boolean function Implementation using Mux | 53 |
| 19 | FA using Mux and Mux tree | 62 |
| 20 | Demultiplexers | 42 |
| 21 | Decoders | 41 |
| 22 | Decoders configurations and priority encoders | 62 |
| 23 | Comparators | 57 |
| 24 | Introduction to sequential logic ckts, Basic storage element (NOR latch) | 69 |
| 25 | NAND latch | 45 |
| 26 | Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems | 84 |
| 27 | Master-Slave combination and Edge triggering Flip flops | 73 |
| 28 | Revision of latch, Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems | 59 |
| 29 | Master-Slave combination and its limitations | 7 |
| 30 | Edge triggering and its advantages | 51 |
| 31 | Asynchronous inputsOverriding inputs of Flip flops, Characteristic equations and Excitation table of Flip flops | 65 |
| 32 | Flip flop conversions | 18 |
| 33 | Applications of the Flip flops (Counters - Asynchronous up and down counters) | 68 |
| 34 | Asynchronous Mod-N counters | 60 |
| 35 | Asynchronous updown counters, Timing considerations of the flip flops and limitations of the Asynchronous counter | 51 |
| 36 | Design of synchronous counters | 87 |
| 37 | Registers, shift registers and its configurations, universal shift registers | 62 |
| 38 | Counters based on shift registers (Ring and Johnson counters) | 51 |
| 39 | Frequency divider circuits | 101 |
| 40 | Frequency multiplier and Edge detector circuits | 36 |
| 41 | Introduction to FSM, Implicit and Explicit FSM | 63 |
| 42 | FSM sequence detector of melay and moore model | 102 |
| 43 | Problems on FSM | 82 |
| 44 | Assignment discussion | 34 |
| 45 | Synchronizers to change the pipelining. | 25 |
| 46 | Synchronizers to change the pipelining. | 102 |
| 47 | FSM-Mealy and moore problems,doubt discussion | 26 |
| 48 | D Flip flop using transmission gate | 165 |
| 49 | ASIC FLOW SES1 | 171 |
| 50 | ASIC FLOW SES2 | 148 |
| 51 | ASIC FLOW SES3 | 170 |
| 52 | ASIC FLOW SES4 | 105 |
| 53 | UNIX SES1 | 125 |
| 54 | UNIX SES2 | 140 |
| 55 | UNIX SES3 | 127 |
| 56 | UNIX SES4 | 50 |
| 57 | UNIX SES5 | 172 |
| 58 | UNIX SES6 | 168 |
| 59 | UNIX SES7 | 156 |
| 60 | UNIX SES8 | 116 |
| 61 | UNIX LAB SES | 87 |
| 62 | UNIX LAB SES | 129 |
| 63 | LINUX GVIM SES | 32 |
| 64 | Need for Transistor? | 25 |
| 65 | How MOSFET function? | 36 |
| 66 | Classification of solids. What makes semiconductor special? | 26 |
| 67 | Intrinsic and Extrinsic semiconductors | 33 |
| 68 | PN Junction diode | 20 |
| 69 | Applications of Diode | 52 |
| 70 | BJT | 62 |
| 71 | FET basics | 54 |
| 72 | MOSFET: PMOS, NMOS, CMOS | 60 |
| 73 | CMOS fabrication | 102 |
| 74 | CMOS short channel effects | 12 |
| 75 | CMOS leakage currents | 85 |
| 76 | FinFET | 20 |
| 77 | TCL Cygwin usage basics | 20 |
| 78 | TCL traning overview, Agenda | 40 |
| 79 | Introduction to TCL | 58 |
| 80 | How to run the TCL program | 50 |
| 81 | Formal syntax of the TCL | 37 |
| 82 | set, puts and gets commands | 87 |
| 83 | TCL Operators | 58 |
| 84 | TCL Control statements | 63 |
| 85 | TCL Control statements (if and for statements) | 31 |
| 86 | TCL Control statements (while statements) | 30 |
| 87 | TCL Control statements (switch and foreach statements) | 24 |
| 88 | TCL strings and its operators | 68 |
| 89 | Strings operators Conti... | 64 |
| 90 | Examples of Strings operators Conti... | 55 |
| 91 | Programs on TCL Strings operators | 26 |
| 92 | TCL Lists | 55 |
| 93 | Programs on TCL Lists | 61 |
| 94 | TCL special variables | 30 |
| 95 | Programs on TCL special variables | 35 |
| 96 | Programs on TCL special variables Conti... | 54 |
| 97 | TCL File handling operations | 59 |
| 98 | Programs on TCL File handling operations | 56 |
| 99 | Programs on TCL File handling operations Conti... | 82 |
| 100 | TCL Procedures and Programs on TCL Procedures | 50 |
| 101 | TCL Procedures and Programs on TCL Procedures Conti... | 52 |
| 102 | TCL Procedures and its parameters | 47 |
| 103 | TCL Arrays | 47 |
| 104 | TCL Associative Arrays | 33 |
| 105 | Programs on TCL Arrays | 105 |
| 106 | TCL Dictionary | 48 |
| 107 | TCL Regular expression | 48 |
| 108 | Programs on TCL Regular expression | 46 |
| 109 | Programs on TCL Regular expression Conti... | 46 |
| 110 | Programs on TCL Regular expression Conti... | 92 |
| 111 | PD BASICS SES1 | 120 |
| 112 | PD BASICS SES2 | 167 |
| 113 | PD BASICS SES3 | 140 |
| 114 | PD BASICS SES4 | 105 |
| 115 | PD BASICS SES5 | 132 |
| 116 | PD BASICS SES6 | 113 |
| 117 | PD BASICS SES7 | 110 |
| 118 | PD BASICS SES8 | 70 |
| 119 | fkf Introduction to digital system | 10 |
| 120 | ASIC Design flow | 149 |
| 121 | Factors affecting delay and Power in CMOS | 126 |
| 122 | Input file - .lib file | 106 |
| 123 | Input file - .lef file | 73 |
| 124 | Input file - .tf and tlu+ file | 75 |
| 125 | Netlist and Hireachial design | 90 |
| 126 | Creating Core area and Die Area | 92 |
| 127 | Port Placement | 43 |
| 128 | TCL Program for Port Placement using Different Commands | 98 |
| 129 | Macros and Type of Macros | 121 |
| 130 | Macro Placement Guide lines | 47 |
| 131 | Blockages and Keepout Margin | 31 |
| 132 | Power Reduction Techniques - Multi Voltage design | 37 |
| 133 | Power Reduction Techniques - Multi Vt Cells | 10 |
| 134 | Power Reduction Techniques - Clock gating Design | 14 |
| 135 | UPF For Multivoltage design | 87 |
| 136 | Power Reduction Techniques - Power gating design | 71 |
| 137 | End cap cells | 35 |
| 138 | TAP cells , TIE Cells DCAP and Spare cells | 85 |
| 139 | Power Planning | 92 |
| 140 | Sanity Checks at each stage and basics of timing | 184 |
| 141 | Setup and Hold Analysis | 57 |
| 142 | In to reg and reg to out path discussion | 141 |
| 143 | PBA and GBA paths | 115 |
| 144 | Timing Exceptions | 67 |
| 145 | Uncertainity , Skew , transition and Driving cell | 82 |
| 146 | Placement goals and checks before placement stage | 93 |
| 147 | Inputs to placement and Placement steps | 120 |
| 148 | Placement Optimization Techniques | 189 |
| 149 | CTS and Clock gating cells | 123 |
| 150 | CTS spec and Clock tree exceptions | 98 |
| 151 | CTS steps and CRPR | 141 |
| 152 | Routing | 130 |
Curriculum
| Specification |
| RTL coding, lint checks |
| RTL integration |
| Connectivity checks |
| Functional Verification |
| Synthesis & STA |
| Gate level simulations |
| Power aware simulations |
| Placement and Routing |
| DFT |
| Custom layout |
| Post silicon validation |
| Conductors, Semiconductors, Insulators |
| Intrinsic and Extrinsic Semiconductors |
| Diode |
| BJT |
| MOSFET (NMOS, PMOS, CMOS) |
| FinFET |
| Device Fabrication |
| Significance of above aspects with Physical Design flow |
| Shells |
| File and directory management |
| User administration |
| Environment variables |
| Commonly used commands |
| Shell scripting basics |
| SEd and AWK |
| Revision management |
| Makefiles |
| Digital Design basics |
| combinational logic |
| sequential logic, FF, latch, counters |
| Memories |
| Setup time, Hold time, timing closure, fixing setup time and hold time violations |
| STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations |
| www.vlsiguru.com/digital-design-complete |
| Introduction to all the majorly used keywords on PD flow |
| VLSI Technology concepts |
| Resistance, Capacitance, Inductance |
| Parasitic capacitance |
| L-C-R circuit analysis |
| RC circuit significance with circuit delay |
| Clock distribution concepts, skew |
| Introduce TCL |
| Why TCL? |
| TCL Script Processing |
| Understand TCL uses and strengths |
| Writing simple TCL scripts |
| TCL for VLSI scripting |
| TCL : Main Features |
| TCL in EDA |
| TCL shell (tclsh) |
| Working with TCL scripts (UNIX) |
| TCL Interpreter in SoC Design Tools |
| TCL Scripting for SoC Design |
| TCL Commands |
| Variables |
| Substitution and Command Evaluation |
| Operators |
| Mathematical Functions |
| Procedures |
| Control flow : if, if-else, switch, for, foreach, while, break and continue |
| string, string operations |
| List, List manipulation |
| Arrays, array methods |
| Working with files |
| Command line arguments |
| Regular expressions |
| Complete TCL Scripts |
| TCL Packages |
| Basics of Synthesis |
| High Level Synthesis Flow |
| Reading of Verilog RTL File |
| Target and Link Libraries |
| Resolving References with Link Libraries |
| Reading hierarchical Designs |
| Reading ddc design |
| Analyse & Elaborate Commands |
| Constraining and Compiling RTL |
| Post Synthesis Output Data |
| Constraining Register to Register Paths |
| Constraining Inputs Paths |
| Constraining Outputs Paths |
| Virtual Clock |
| Load Budgeting |
| Default Path Groups |
| Creating User-defined Path Groups |
| Prioritizing Path Groups |
| Timing Reports |
| Analyzing Timing Reports |
| Defining a Clock with additional options |
| Input Delay with additional options |
| Output Delay with additional options |
| Pre-CTS versus Post CTS Clock Latencies |
| Independent IO Latencies |
| Output Delay with Network Latency |
| Output Delay with Source Latency |
| Different IO versus Internal Latencies |
| IO Clock Latencies |
| Handling Different IO Vs Internal Latencies |
| Virtual External Clock Latencies |
| Included External Clock Latencies |
| Multiple Synchronous Clocks |
| Multiple Clocks Input Delay |
| Maximum Internal Input Delay |
| Multiple Clock Output Delay |
| Maximum Internal Output Delay |
| Inter Clock Uncertainty |
| Generated Clocks |
| Mutual Exclusive Synchronous Clocks |
| Logically Exclusive Clocks |
| Multiple Clocks per Register |
| Cross Talk Analysis |
| Asynchronous Clocks |
| Multi Cycle Paths and Constraints |
| High Level Multi-Voltage Design Concepts |
| Supplies and Power Domains |
| Power Ports and Nets |
| Level Shifters |
| Power States and PS Table |
| IC Compiler II Library Manager |
| ICC Compiler II NDM Cell Library |
| Cell Library Characteristics |
| Library Manager Flow |
| Tech Only NDM Library |
| Technology-Only Library Flow |
| Technology File |
| Read TLU+ Files |
| Tech Library Preparation |
| Top Level, Sub-System Level and Block Level Design Setup |
| Set up initial Design Implementation |
| Loading Netlist from Synthesis |
| Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files |
| Flow Setup and Design Setup |
| Loop-back to Synthesis for Correlation issues correction |
| Top Level, Sub-System Level and Block Level Design Setup |
| Set up initial Design Implementation |
| Loading Netlist from Synthesis |
| Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files |
| Flow Setup and Design Setup |
| Loop-back to Synthesis for Correlation issues correction |
| Initial Floorplanning settings |
| Define Pad Instances (Physical Cells) |
| Pad Instance co-ordinates |
| Start Floorplaning |
| Core Die Size setting |
| Floorplanning of Pad Instances |
| Pad Filler Insertion |
| Define Pad Ring Power Grid |
| Macro Instance constraints |
| Macro Instance Array creation |
| Macro Instance Orientation |
| Anchor based and Relative Placement of Macro Instances |
| Macro Instance-Channel settings |
| Macro Instance placement - Manual |
| Congestion probability around Macro Instances |
| Defining Placement Blockages |
| Running placement |
| Defining placement strategies |
| In Place Optimization |
| Hierarchical Placement |
| Relative Placement |
| Congestion analysis and reduction |
| Macro placement changes to reduce congestion |
| Standard Cell Placement Constraints |
| Halo creation for instances |
| Congestion Analysis with Standard Cell placement |
| Local Congestion Reduction |
| Density Screen and Placement Blockage for Standard Cells |
| Congestion Aware Placement |
| Re-Check Macro Placement for better Congestion relief |
| Create Balanced Buffer Trees for High Fanout Net |
| Defining Power Structure |
| Logical Power/Ground Connections |
| Setting Power Network Constraints |
| Create and Analyze Power Structure |
| Change Power Constraints and Re-Createto meet IR requirements |
| Power Ground Pin connection and create Power Rails |
| Power Network Checks for IR and Resistance |
| Placement Blockage for Power Network |
| Incremental Placement |
| Re-Order Scan connectivity within Chain |
| Re-Partition Scan connectivity across Chains |
| SCANDEF file based Scan Chain Re-Ordering |
| Congestion checks for Overflow again |
| RC extraction for Net Parasitics |
| Check Timing for Max Analysis |
| Run Timing/Congestion aware Placement |
| Logic Re-Structuring for Placement and Timing |
| Check Pre-CTS timing based on Global Routing and Detailed Placement |
| Setting Clock Constraints such as Target Skew Target Insertion Delay |
| Clock Root Attributes as Stop, Float and Exclude Pins |
| Building for Generated and Gated Clocks |
| Don't Touch attribute on existing Clock Tree structure |
| Defining Clock Buffers and Inverters. |
| Set Clock Tree Timing DRCs. |
| Non-Default Clock Routing rules setting |
| Perform Clock Tree Synthesis and Clock Tree Optimization |
| Reduce Hold Violations in Data paths and Scan Paths |
| Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners |
| Synchronous Clock Balancing |
| Cross-Clock Delay Balancing |
| Logical Hierarchy aware CTS |
| Max and Min Analysis and subsequent Optimization |
| Fixing Violations |
| CTS Optimization across other modes and PVT corners (MMMC) |
| Skew and Insertion Delay checks |
| Checking Crosstalk on Clock Network |
| Pre-Route check points |
| Routing fundamentals |
| Global Route |
| Detail Routing |
| Track Assignment and Route |
| Refining Detailed Route |
| Over the Macro routing |
| Non-Preferred Routing direction |
| Clock Net Routing |
| Initial Data path routing |
| Redundant VIA insertion setting |
| Post Detailed Route Optimization |
| Fixing DRC Violations |
| Post Detailed Route Delay Calculation Algorithms |
| Crosstalk Delay and Noise Analysis and Fix |
| Check Leakage Power Dissipation |
| VT Cell swap for power and timing trade-off |
| Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD |
| Reduce Dynamic power |
| Meet Total Power target |
| Functional ECO |
| Timing ECO |
| Metal Only ECO using Spare Cells for base frozen designs |
| 2 Hands on projects covering detailed flow from Synthesis, input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification |
| Projects based on multi voltage domain |
| Student will be working on 3rd project independently with trainer/mentor support. |
| Antenna Rules and Fixes |
| Critical Area Analysis |
| Wire Spreading and widening |
| Setting minimum metal jog length |
| Filler Cell Insertion |
| Metal Fill |
| Timing Checks after Metal Fill |
| Parasitic Extraction for SignOff timing analysis |
| Export Netlist |
| Export GDSII |
| Facing interviews effectively |
| Industry work culture |
| Group discussions |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Dedicated Trainer Accessible On Phone / Email / Whatsapp
- Trainer Exp: 15 Years
Price - ₹45,000 + GST
₹50,000 (10% Off)
10 hours left to avail at this price
Course Highlights
- Mentor Support for doubt clarifications
- Product company focused questions
- 50+ hours of lectures
TESTIMONIALS
What Our Students Says About Inskill
I joined this institute in summer after I was admissioned into IIT MADRAS, some of my seniors done training in this institute so they suggested me. When I was joining this institute my aim was to learn hardware language so that at the time of placements I should have some extra skills to stand out from the crowd and when the placement came I was so clear about my conceepts and the interviewers got impressed..they provided training live and I was able to clear my doubts and it also helped in courses in IIT which was a hectic thing for others.
The best thing about the institute is that the head of the institute teaches us one to one and make everything a cakewalk.
To be honest I didn't have any prior coding experience before
I am placed in Analog Devices Inclusive at very handsome package on Day 1 placements .
Thanks for the support.
The course at VLSI GURU very well structured and adequate for a fresher to get into VLSI domain. At VLSI GURU trained us using recorded lectures, live classes and mentor sessions ,assingments give us multiple chances to learn and doubt solving .They also provide labs and projects helped me gaining practical knowledge on the concepts .They cover every topic from basics . they conduct mock interview sessions and resume building sessions,which prepared us well for job interview
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I recently completed the Functional Verification course at VLSIGuru, and I must say it was an exceptional training experience.
The course content was comprehensive, covering all essential aspects of functional verification.
The instructors were highly knowledgeable and provided clear explanations,making complex concepts easy to understand.
The practical hands-on exercises and real-world examples greatly enhanced my learning and problem-solving skills.
The course structure was well-organized, allowing for a smooth progression from fundamentals to advanced topics.
Overall, VLSIGuru's Functional Verification course has equipped me with the necessary skills and confidence to excel in the field.
Highly recommended!
FAQ
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