Specification & Design Flow

• Specification
• RTL Coding & Lint Checks
• RTL Integration
• Connectivity Checks
• Functional Verification
• Synthesis & STA
• Gate Level Simulations
• Power Aware Simulations
• Placement and Routing
• DFT
• Custom Layout
• Post Silicon Validation

Transistors in Hardware Design

• Significance of transistors in hardware design
• Logic gate implementation using BJT, CMOS
• MOSFET functionality

Semiconductors

• What makes Semiconductor special element?
• Classification of solids into three types
• Conductor, Insulator, Semiconductor
• Energy bands in Solids
• Types of Semiconductors
• Intrinsic Semiconductors
• Extrinsic Semiconductors
• Types of Extrinsic Semiconductors
• N-type Extrinsic Semiconductor
• P-type Extrinsic Semiconductor
• Si, Ge – comparison
• Types of current in Semiconductors – Drift, Diffusion
• Ion

PN Junction Diode

• PN Junction – forward, reverse bias
• V-I Characteristics of PN Junction Diode
• Different types of Diode
• Applications of Diode

BJT

• BJT
• BJT working principle
• How BJT can be used for large scale manufacturing
• BJT fabrication steps
• Types of BJT
• Why BJT is not used in lower technology nodes
• Issues with BJT
• Advantages of BJT
• NAND gate using BJT

Field Effect Transistor (FET)

• What is Field Effect Transistor?
• Types of FET
• NMOS
• PMOS
• CMOS
• Fin

NMOS

• What is NMOS?
• NMOS working principle
• Different voltages, currents, their equations
• NMOS circuit representation
• How NMOS works like a switch
• How NMOS can be used for large scale manufacturing
• NMOS fabrication steps
• Types of NMOS
• Why CMOS is used instead of NMOS
• Issues with NMOS
• Advantages of NMOS
• NAND gate using NMOS

CMOS

• What is CMOS?
• CMOS working principle
• Different voltages, currents, their equations
• CMOS circuit representation
• How CMOS works like a switch
• How CMOS can be used for large scale manufacturing
• CMOS fabrication steps
• Types of CMOS
• Issues with CMOS
• Advantages of CMOS
• NAND gate using CMOS
• CMOS second order effects

FinFET

• What is FinFET?
• FinFET working principle
• Different voltages, currents, their equations
• Circuit representation
• How FinFET works like a switch
• How FinFET can be used for large scale manufacturing
• FinFET fabrication steps
• Types of FinFET
• Issues with FinFET
• Advantages of FinFET
• NAND gate using FinFET
• FinFET second order effects

• Layers of CMOS
• Depositing Oxide Layer
• Photolithography
• Masking
• Etching Layers
• Formation of N-Well
• Self-Aligned Gate Fabrication Process
• Diffusion to Create N+ and P+ Regions
• Metallization

Combinational Logic

• Number Systems
• Radix Conversions
• K-Maps, Min-terms, Max Terms
• Logic Gates
• Realization of Logic Gates using MUXs and Universal Gates
• Complements (1’s / 2’s / 9’s / 10’s Complement)
• Arithmetic Operations using Complements
• Boolean Expression Minimization, DeMorgan Theorems
• POS and SOP
• Conversion and Realization
• Adders
  • Half Adder
  • Full Adder
• Subtractors
  • Half Subtractor
  • Full Subtractor
• Multiplexers
• Realizing Bigger MUXs using Smaller MUXs
• Implementing Adders and Subtractors using Multiplexers
• Decoders and Encoders
• Implementing Decoders and Encoders using MUX and DEMUX
• Bigger Decoder/Encoder using Smaller Decoder/Encoder
• Comparators
• Implementing Multi-bit Comparators using 1-bit Comparator

Sequential Logic

• Latch, Flip-Flop
• Latch, Flip-Flop using Gates or MUXs
• Different Types of Flip-Flops
• Flip-Flop Truth Table
• Excitation Tables
• Realization of Flip-Flops using Other Flip-Flops
• Applications of Flip-Flops and Latches
  • Counters
  • Shift Registers
  • Synchronizers for Clock Domain Crossing
  • FSMs
  • Mealy and Moore FSM
  • Different Encoding Styles
  • Frequency Dividers
  • Frequency Multiplication
• Static Timing Analysis (STA)
  • Setup Time, Hold Time, Timing Closure
  • Fixing Setup and Hold Time Violations
  • Launch Flop and Capture Flop

• Introduction to majorly used keywords on PD flow
• VLSI Technology concepts
  • Resistance, Capacitance, Inductance
  • Parasitic capacitance
  • L-C-R circuit analysis
  • RC circuit significance with circuit delay
• Clock distribution concepts, skew

• Installing Linux platform in Windows
• Linux Basics
• Linux versus Windows
• Linux Terminal
• File and Directory Management
• Changing File Permissions
• Absolute Path and Relative Path
• Working with Directories
• GVIM – Major Keyboard Shortcuts
• Text Display Commands
• Root Configuration Files
• Environment Variables
• Text Processing Commands
  • grep, fgrep
  • xargs
  • SED
  • AWK
  • Pipes and Filters
• Connecting to Server
• Process Management
• LSF
• Ping
• FTP
• CTAGs
• File Compress and Extract
• Soft Links

• Overview
• Env Setup
• Special Variables
• Data Types
• Variables
• Operators
• Decisions
• Loops
• Arrays, Strings, Lists, Dictionary
• History and Redoing of Commands
• String Pattern Matching Commands

• Basics of Synthesis
• High Level Synthesis Flow
• Reading of Verilog RTL File
• Target and Link Libraries
• Resolving References with Link Libraries
• Reading Hierarchical Designs
• Reading DDC Design
• Analyze & Elaborate Commands
• Constraining and Compiling RTL
• Post Synthesis Output Data

• Constraining Register to Register Paths
• Constraining Input Paths
• Constraining Output Paths
• Virtual Clock
• Load Budgeting
• Default Path Groups
• Creating User-defined Path Groups
• Prioritizing Path Groups
• Timing Reports
• Analyzing Timing Reports
• Defining a Clock with Additional Options
• Input Delay with Additional Options
• Output Delay with Additional Options
• Pre-CTS versus Post-CTS Clock Latencies
• Independent IO Latencies
• Output Delay with Network Latency
• Output Delay with Source Latency
• Different IO versus Internal Latencies
• IO Clock Latencies
• Handling Different IO vs Internal Latencies
• Virtual External Clock Latencies
• Included External Clock Latencies
• Multiple Synchronous Clocks
• Multiple Clocks Input Delay
• Maximum Internal Input Delay
• Multiple Clock Output Delay
• Maximum Internal Output Delay
• Inter Clock Uncertainty
• Generated Clocks
• Mutual Exclusive Synchronous Clocks
• Logically Exclusive Clocks
• Multiple Clocks per Register
• Cross Talk Analysis
• Asynchronous Clocks
• Multi Cycle Paths and Constraints

• High Level Multi-Voltage Design Concepts
• Supplies and Power Domains
• Power Ports and Nets
• Level Shifters
• Power States and PS Table

• IC Compiler II Library Manager
• ICC Compiler II NDM Cell Library
• Cell Library Characteristics
• Library Manager Flow
• Tech Only NDM Library
• Technology-Only Library Flow
• Technology File
• Read TLU+ Files
• Tech Library Preparation

• Top Level, Sub-System Level and Block Level Design Setup
• Set Up Initial Design Implementation
• Loading Netlist from Synthesis
• Setting Path to .lib Files, LEFs, DEFs (if needed), Technology Files, SDC Files
• Flow Setup and Design Setup
• Loop-back to Synthesis for Correlation Issues Correction

• Initial Floorplanning Settings
• Define Pad Instances (Physical Cells)
• Pad Instance Coordinates
• Start Floorplanning
• Core Die Size Setting
• Floorplanning of Pad Instances
• Pad Filler Insertion
• Define Pad Ring Power Grid
• Macro Instance Constraints
• Macro Instance Array Creation
• Macro Instance Orientation
• Anchor-Based and Relative Placement of Macro Instances
• Macro Instance Channel Settings
• Macro Instance Placement – Manual
• Congestion Probability Around Macro Instances
• Defining Placement Blockages

• Running Placement
• Defining Placement Strategies
• In-Place Optimization (IPO)
• Hierarchical Placement
• Relative Placement
• Congestion Analysis and Reduction
• Macro Placement Changes to Reduce Congestion
• Standard Cell Placement Constraints
• Halo Creation for Instances
• Congestion Analysis with Standard Cell Placement
• Local Congestion Reduction
• Density Screen and Placement Blockage for Standard Cells
• Congestion Aware Placement
• Re-Check Macro Placement for Better Congestion Relief
• Create Balanced Buffer Trees for High Fanout Net

• Defining Power Structure
• Logical Power/Ground Connections
• Setting Power Network Constraints
• Create and Analyze Power Structure
• Change Power Constraints and Re-Create to Meet IR Requirements
• Power/Ground Pin Connection and Create Power Rails
• Power Network Checks for IR and Resistance
• Placement Blockage for Power Network
• Incremental Placement

• Re-Order Scan Connectivity within Chain
• Re-Partition Scan Connectivity across Chains
• SCANDEF File-Based Scan Chain Re-Ordering

• Congestion Checks for Overflow Again
• RC Extraction for Net Parasitics
• Check Timing for Max Analysis
• Run Timing/Congestion Aware Placement
• Logic Re-Structuring for Placement and Timing

• Check Pre-CTS Timing Based on Global Routing and Detailed Placement
• Setting Clock Constraints such as Target Skew and Target Insertion Delay
• Clock Root Attributes as Stop, Float and Exclude Pins
• Building for Generated and Gated Clocks
• Don’t Touch Attribute on Existing Clock Tree Structure
• Defining Clock Buffers and Inverters
• Set Clock Tree Timing DRCs
• Non-Default Clock Routing Rules Setting
• Perform Clock Tree Synthesis and Clock Tree Optimization
• Reduce Hold Violations in Data Paths and Scan Paths
• Clock Tree Building/Optimization for Multiple Modes and Multiple PVT Corners
• Synchronous Clock Balancing
• Cross-Clock Delay Balancing
• Logical Hierarchy Aware CTS
• Max and Min Analysis and Subsequent Optimization
• Fixing Violations
• CTS Optimization Across Other Modes and PVT Corners (MMMC)
• Skew and Insertion Delay Checks
• Checking Crosstalk on Clock Network

• Pre-Route Check Points
• Routing Fundamentals
• Global Route
• Detailed Routing
• Track Assignment and Route
• Refining Detailed Route
• Over-the-Macro Routing
• Non-Preferred Routing Direction
• Clock Net Routing
• Initial Data Path Routing
• Redundant VIA Insertion Setting
• Post Detailed Route Optimization
• Fixing DRC Violations
• Post Detailed Route Delay Calculation Algorithms
• Crosstalk Delay and Noise Analysis and Fix

• Check Leakage Power Dissipation
• VT Cell Swap for Power and Timing Trade-Off
• Analyzing Dynamic Power Dissipation Based on GAF, SAIF, VCD
• Reduce Dynamic Power
• Meet Total Power Target

• Functional ECO
• Timing ECO
• Metal-Only ECO Using Spare Cells for Base Frozen Designs

• Projects covering detailed flow from Input Files, Floorplan, Power Planning, Placement, CTS, Routing, SPEF Extraction, STA, and Physical Verification
  • One Project Completely Guided by the Trainer
  • Other Project Done by Student with Trainer Guidance
• Project Based on Multi-Voltage Domain

• Antenna Rules and Fixes
• Critical Area Analysis
• Wire Spreading and Widening
• Setting Minimum Metal Jog Length
• Filler Cell Insertion
• Metal Fill
• Timing Checks After Metal Fill
• Parasitic Extraction for Signoff Timing Analysis
• Export Netlist
• Export GDSII