Power Aware(Low power) Verification Training

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Power Aware(Low power) Verification Training

About Course

Power consumption is significant aspect of increasingly complex SOCs, which are typically used for portable systems. Low power design techniques helps identify the power behavior and minimise the power consumption. Both portable and non-portable systems, requires efficient power management techniques.

This course introduces IEEE 1801 UPF for specifying the idle power management architecture.
Student will learn SoC power domain architecture , in UPF how to define power intent - supply_port, supply_net, power cells like power switches, isolation cells, level shifters , retention cells, power state table and gating logic. They will also learn how to update a design for the power intent, run the simulation to analyse the power behavior.

Demo Videos

Unit NumberTopicDuration (Mins)
1Low power UPF training agenda3
2What is power management?28
3Types of power consumption?21
4Low power techniques52
5Clock gating3
6SOC power architecture43
7Revision21
8UPF concepts24
9Functional intent Vs Power intent7
10State retention47
11UPF power intent commands53
12Revision25
13Memory controller UPF strategy26
14Memory ctrl testbench setup79
15Memory controller power aware simulation debug120
Curriculum

Power Management – Need for low power
Types of Power consumption
Understanding CMOS and FinFET technology w.r.t types of power consumption
Impact of technology shrinking on Vt
Technology Scaling Vs Power
Low power techniques
Leakage power reduction techniques
Dynamic power reduction techniques
Understanding power architecture of SOC
PMIC: Power Management Integrated Circuit
PMU – Power management unit
PMIC and SOC interfacing
CPUSS – power architecture
Verification goals in power aware simulations
UPF History and commands
UPF Design Data Flow
Functional Intent Vs Power Intent
Power Intent
Power Domain
Retention register design
  • Single control live slave
  • Dual control Balloon
  • Single control Balloon
  • Retention Register relative layouts
Storing the data during block power-down (Power Gating)
Memory Retention methods
Power Distribution
Power states
Sim states
Verification of state retention logic in RTL
UPF Power intent commands
Steps for running power aware simulations
UPF TB setup
Memory controller architecture
Memory controller low power verification setup
Running low power simulations
Low power simulations issues.
Debugging low power issues
Low power assertions and coverage

Benefits of eLearning?
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Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹7000 + GST

₹8,800    (25% Off)

10 hours left to avail at this price

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FAQ

  1. Course presentations for all topics
  2. Session notes
  3. Lab documents with detailed steps
  4. User guides

  1. DV engineers who wants to diversify their verification domain expertise.

  1. Understanding of SoC architectures, Verification of designs.

  1. Yes. It is issued once student completes all the course assignments.