System Verilog functional coverage and code coverage, Assertions training

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System Verilog functional coverage and code coverage, Assertions training

About Course

System Verilog coverage and assertions training (VG-SV) course is a 4 weeks course structured to enable engineers gain expertize in functional coverage, code coverage and assertions.

Training will include hands on lab for coverage analysis and assertion development and debug.

All the aspects of coverage analysis will be covered including individual coverage types, debugging the coverage holes. Assertion training will involve in-depth exposure to assertion coding and failure debug

Demo Videos
Unit NumberTopicDuration (Mins)
1Functional Coverage, Need of Functional Coverage, Functional Coverage Implementation, Functional Coverage Types, Functional Coverage Report Analysis, Code Coverage, Code Coverage Report Generation.233
2Code Coverage Analysis, Code Coverage Types, UCDB, Code Coverage Example, Assertions235
3Assertion Examples67
4SV Assertions: Concurrent asssertions55
5SV Assertions: Asssertion layers, sequences79
6SV Assertions: Asssertion examples80
7SV Assertions: Sequence Operators : Matching, repetition101
8SV Assertions: Asssertion practical examples: AXI, memory, FSM, Power management block121
Curriculum

Benefits of eLearning?

 

  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹4,000 + GST

₹4,500    (10% Off)

10 hours left to avail at this price

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