Synthesis and STA Training with hands on project

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Synthesis and STA Training with hands on project

Synthesis and STA Training is a 4 months course, provides the participants with in depth exposure to both Synthesis and complete Timing SignOff strategies for successful and confident Tape-Out of the Design to the Semiconductor Fabrication House.

Synthesis Training:

Synthesis training includes all the aspects starting from HDL modelling, Synthesis flow, Constraints, analysing and debugging the results, optimization techniques, report generation and hands on projects to understand the Synthesis complete flow.

Demo Videos

Unit NumberTopicDuration (Mins)
1CMOS , Delay , Transition time, Power98
2Basics of Synthesis100
3Input files for PD105
4Basics of PD flow148
5Clock transition , Clock latency and clock skew145
6Setup Analysis143
7Hold Analysis170
8In to reg and reg to out , Types of clocks in design111
9Tool Installation Support and input file discussion162
10PVT conditions , Corners and Explanation of .lib182
11Synthesis Flow . LAB143
12Some usefull synthesis commands and Types of clocks129
13Writing Basic SDC file165
14Discussion on power reduction techniques170
15UPF for multi voltage design123
16Setup Fixing methods and Level shifter analysis130
17Floorplan In ICC2143
18Physical Aware Synthesis166
19Func mode , Test mode and Multi cycle path217
20Writing SDC for different Modes , corners and scenarios147
21Writing SDC for different Modes , corners and scenarios135
22Check_Timing - Hands on discussion160
23Discussion on Synthesis optimization techniques200
24Clock gating check and Handling asynchronus signals132
25Timing Analysis at placement stage143
26Timing Analysis at CTS stage146
27Useful skew - hands130
28Cross talk147
29Shielding and inputs to extract SPEF127
30SPEF extraction using STARRC74
31DMSA flow in Prime time166
Fee Structure
Curriculum

Import design
Understanding Liberty file
Synthesis flow
Writing Synopsys design constraints file
Multi voltage design and UPF
Physical aware synthesis
Synthesis optimization techniques
Synthesis hands on using tool DC Shell
Latency, skew and timing paths
• Setup Violation
• Hold Violation
• In_to_reg paths
• reg_to_out paths
Derate and its Types
• Derate Overview
PVT and MCMM
• PVT Corners
• MCMM Concepts
• Writing MCMM File
Special Timing Paths
• Multicycle Path
• Half Cycle Path
Clock Domain Crossing (CDC)
• Recovery and Removal Checks
• Synchronizers
Path Grouping
Useful Skew
• Clock Push and Clock Pull
• Time Borrowing
Cross Talk Effects
• Cross Talk Noise
• Cross Talk Delay
Design Analysis Tools
• Design Analysis using ICC2 or Fusion Compiler (FC)
• SPEF Extraction using StarRC
PrimeTime Lab
• Input for PrimeTime
• Analysis Coverage
• Check Timing
• Cross-talk Analysis
• Timing Fixing Methods
• Physical Aware ECO
• PrimeTime DMSA Flow

Benefits of eLearning?
  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹29,000 + GST

₹32,500    (10% Off)

10 hours left to avail at this price

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FAQ

  1. Course presentations for all topics
  2. Session notes
  3. Lab documents with detailed steps
  4. User guides

  1. Expertise on Advanced Digital design concepts

  1. Course will involve practical exposure to Synthesis and STA with 2 hands on projects. Every session will have theory with supporting labs.

  1. Each session of course is recorded, missed session videos will be shared

  1. Yes, You will have option to view the recorded videos of course for the sessions missed
  2. You will have option to repeat the course any time in next 1 year

  1. Yes, Course fee also includes support for doubt clarification sessions even after course completion
  2. You have option to mail you queries
  3. Option to meet in person to clarify doubts