Synthesis Training covers the aspect of converting the design in form of RTL into Technology mapped netlist. Synthesis is an algorithm intensive task consisting of many stages within it requiring various inputs in order to produce a functionally correct netlist. The main part of Synthesis Training consists of reading in the design, converting RTL to Boolean equations through elaboration, then converting the Boolean equations to Generic Mapped Cells and then technology mapped cells from library, setting constraints, optimizing the design, analyzing the results and saving the design database for Placement and Routing stage to take on. Candidates who are interested in exploring opportunities in Synthesis and Front-end STA can undergo this in-depth Synthesis training to get good understanding of RTL constructs, Gate level Netlist, Constraint Development, Latch based designs, pipe lining and re-timing, basic Scan stitching, Setup timing closure, Topography based logic re-structuring, Wire Load Models, Logical Equivalence Checks. Hierarchical Synthesis is another key feature covered in this Synthesis Training Cadence Implementation Suite for Synthesis (as RTL Compiler / Genus) would be used in this Synthesis Training program. Candidates would get hands on work on two full designs.

Synthesis Training Topic covered.
Introduction to synthesis.
Reading RTL in HDL form, dotlibs, SDC
Different types of RTL constructs
Analyzing dotlib files
Elaboration and Generic Synthesis
Understanding DesignWare components and Logical Operators
Clock gating insertion for reducing Dynamic power post CTS
Creating list of dont_touch and dont_use cells
Technology mapped Synthesis and optimization
Scan Insertion techniques
Checking Design for number of instances, area estimate
Check clock reaching clock pins of flops, unclocked flops
Time borrowing concepts for latch based paths
Leakage variants of standard cells LVT, RVT, HVT
Constraints on logical hierarchy boundaries
Setting Max Transition, Max Capacitance, Max Fanout
Push down and pull up timing constraints
Master clocks and generated clocks in design
Estimating uncertainty values, input and output delays in SDC
False path, Multi cycle path exceptions.
Disabling timing loops in design
Logical Equivalence Checking fundamentals (Top level and Hierarchical)
Hand off database to PnR