Synthesis and STA Training is a 4 months course, provides the participants with in depth exposure to both Synthesis and complete Timing SignOff strategies for successful and confident Tape-Out of the Design to the Semiconductor Fabrication House.
Synthesis Training:
Synthesis training includes all the aspects starting from HDL modelling, Synthesis flow, Constraints, analysing and debugging the results, optimization techniques, report generation and hands on projects to understand the Synthesis complete flow.
Unit Number | Topic | Duration (Mins) |
1 | CMOS , Delay , Transition time, Power | 98 |
2 | Basics of Synthesis | 100 |
3 | Input files for PD | 105 |
4 | Basics of PD flow | 148 |
5 | Clock transition , Clock latency and clock skew | 145 |
6 | Setup Analysis | 143 |
7 | Hold Analysis | 170 |
8 | In to reg and reg to out , Types of clocks in design | 111 |
9 | Tool Installation Support and input file discussion | 162 |
10 | PVT conditions , Corners and Explanation of .lib | 182 |
11 | Synthesis Flow . LAB | 143 |
12 | Some usefull synthesis commands and Types of clocks | 129 |
13 | Writing Basic SDC file | 165 |
14 | Discussion on power reduction techniques | 170 |
15 | UPF for multi voltage design | 123 |
16 | Setup Fixing methods and Level shifter analysis | 130 |
17 | Floorplan In ICC2 | 143 |
18 | Physical Aware Synthesis | 166 |
19 | Func mode , Test mode and Multi cycle path | 217 |
20 | Writing SDC for different Modes , corners and scenarios | 147 |
21 | Writing SDC for different Modes , corners and scenarios | 135 |
22 | Check_Timing - Hands on discussion | 160 |
23 | Discussion on Synthesis optimization techniques | 200 |
24 | Clock gating check and Handling asynchronus signals | 132 |
25 | Timing Analysis at placement stage | 143 |
26 | Timing Analysis at CTS stage | 146 |
27 | Useful skew - hands | 130 |
28 | Cross talk | 147 |
29 | Shielding and inputs to extract SPEF | 127 |
30 | SPEF extraction using STARRC | 74 |
31 | DMSA flow in Prime time | 166 |
Import design |
Understanding Liberty file |
Synthesis flow |
Writing Synopsys design constraints file |
Multi voltage design and UPF |
Physical aware synthesis |
Synthesis optimization techniques |
Synthesis hands on using tool DC Shell |
Latency, skew and timing paths |
• Setup Violation |
• Hold Violation |
• In_to_reg paths |
• reg_to_out paths |
Derate and its Types |
• Derate Overview |
PVT and MCMM |
• PVT Corners |
• MCMM Concepts |
• Writing MCMM File |
Special Timing Paths |
• Multicycle Path |
• Half Cycle Path |
Clock Domain Crossing (CDC) |
• Recovery and Removal Checks |
• Synchronizers |
Path Grouping |
Useful Skew |
• Clock Push and Clock Pull |
• Time Borrowing |
Cross Talk Effects |
• Cross Talk Noise |
• Cross Talk Delay |
Design Analysis Tools |
• Design Analysis using ICC2 or Fusion Compiler (FC) |
• SPEF Extraction using StarRC |
PrimeTime Lab |
• Input for PrimeTime |
• Analysis Coverage |
• Check Timing |
• Cross-talk Analysis |
• Timing Fixing Methods |
• Physical Aware ECO |
• PrimeTime DMSA Flow |
TESTIMONIALS
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Curabitur laoreet cursus volutpat. Aliquam sit amet ligula et justo tincidunt laoreet non vitae lorem. Aliquam porttitor tellus enim, eget commodo augue porta ut. Maecenas lobortis ligula vel tellus sagittis ullamcorperv vestibulum pellentesque cursutu.
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Curabitur laoreet cursus volutpat. Aliquam sit amet ligula et justo tincidunt laoreet non vitae lorem. Aliquam porttitor tellus enim, eget commodo augue porta ut. Maecenas lobortis ligula vel tellus sagittis ullamcorperv vestibulum pellentesque cursutu.
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Curabitur laoreet cursus volutpat. Aliquam sit amet ligula et justo tincidunt laoreet non vitae lorem. Aliquam porttitor tellus enim, eget commodo augue porta ut. Maecenas lobortis ligula vel tellus sagittis ullamcorperv vestibulum pellentesque cursutu.
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Curabitur laoreet cursus volutpat. Aliquam sit amet ligula et justo tincidunt laoreet non vitae lorem. Aliquam porttitor tellus enim, eget commodo augue porta ut. Maecenas lobortis ligula vel tellus sagittis ullamcorperv vestibulum pellentesque cursutu.