• Synthesis Training Overview:

  • Converting RTL design into a technology-mapped netlist.
  • Synthesis is algorithm-intensive with multiple stages and requires various inputs.
  • Main stages include:
    • Reading the design.
    • Converting RTL to Boolean equations through elaboration.
    • Mapping Boolean equations to Generic Mapped Cells and then to technology-mapped cells.
    • Setting constraints, optimizing the design, analyzing results.
    • Saving the design database for Placement and Routing.

• Target Audience:

  • Candidates interested in Synthesis and Front-end STA (Static Timing Analysis).
  • Ideal for those looking to understand RTL constructs, gate-level netlists, constraint development, latch-based designs, pipelining, and timing closure.

• Key Features of Synthesis Training:

  • RTL constructs, gate-level netlist, constraint development.
  • Latch-based designs, pipelining, re-timing, basic scan stitching.
  • Setup timing closure, topography-based logic restructuring.
  • Wire Load Models, logical equivalence checks.
  • Hierarchical synthesis covered.

• Tools Used:

  • Cadence Implementation Suite for Synthesis (RTL Compiler/Genus).

• Hands-on Experience:

  • Candidates will work on two full designs.

• Topics Covered in Synthesis Training:

  • Introduction to Synthesis.
  • Reading RTL in HDL form, dotlibs, and SDC files.
  • Different types of RTL constructs.
  • Analyzing dotlib files.
  • Elaboration and Generic Synthesis.
  • Understanding DesignWare components and logical operators.
  • Clock Gating insertion for reducing dynamic power post CTS.
  • Creating lists of dont_touch and dont_use cells.
  • Technology-Mapped Synthesis and Optimization.
  • Scan insertion techniques.
  • Checking design for number of instances, area estimate.
  • Checking clock pin reachability for flops, detecting unclocked flops.
  • Time Borrowing Concepts for latch-based paths.
  • Leakage variants of standard cells (LVT, RVT, HVT).
  • Constraints on logical hierarchy boundaries.
  • Setting max transition, max capacitance, max fanout.
  • Push-down and pull-up timing constraints.
  • Master clocks and generated clocks in design.
  • Estimating uncertainty values, and input/output delays in SDC.
  • False path and multi-cycle path exceptions.
  • Disabling timing loops in design.
  • Logical Equivalence Checking fundamentals (top-level and hierarchical).
  • Hand-off database to Placement and Routing (PnR).

Logical Equivalence Checking fundamentals (Top level and Hierarchical)
Hand off database to PnR