• PCIe
    ◦ Raw Format
    ◦ Standard 256B End Header Flit Format
    ◦ 68B Flit Format
    ◦ Standard 256B Start Header Flit Format
    ◦ Latency-Optimized 256B with Optional Bytes Flit Format
• CXL 256B Flit Mode
    ◦ Raw Format
    ◦ Latency-Optimized 256B Flit Formats
    ◦ Standard 256B Start Header Flit Format
• CXL 68B Flit Mode
    ◦ Raw Format
    ◦ 68B Flit Format
• Streaming Protocol
    ◦ Raw Format
    ◦ 68B Flit Format
    ◦ Standard 256B Flit Formats
    ◦ Latency-Optimized 256B Flit Formats
• Management Transport Protocol
• Die-to-Die Adapter
• Stack Multiplexing
• Link Initialization
    ◦ Stage 3 of Link Initialization: Adapter Initialization
        ◦ Part 1: Determine Local Capabilities
        ◦ Part 2: Parameter Exchange with Remote Link Partner
        ◦ Part 3: FDI bring up
    ◦ Operation Formats
        ◦ Raw Format for All Protocols
        ◦ 68B Flit Format
            ◦ 68B Flit Format Alignment and Padding Rules
        ◦ Standard 256B Flit Formats
        ◦ Latency-Optimized 256B Flit Formats
        ◦ Flit Format-related Implementation Requirements for Protocol Layer and Adapter
    ◦ Decision Table for Flit Format and Protocol
    ◦ State Machine Hierarchy
    ◦ Power Management Link States
    ◦ CRC Computation
    ◦ Retry Rules
    ◦ Runtime Link Testing using Parity

• Data and Sideband Transmission Flow
    ◦ Byte to Lane Mapping
    ◦ Valid Framing
        ◦ Valid Framing for Retimers
    ◦ Clock Gating
    ◦ Free Running Clock Mode
    ◦ Sideband transmission
        ◦ Sideband Performant Mode Operation (PMO)
    ◦ Lane Reversal
        ◦ Lane ID
    ◦ Interconnect redundancy remapping
        ◦ Data Lane repair
        ◦ Data Lane repair with Lane reversal
        ◦ Data Lane repair implementation
            ◦ Single Lane repair
            ◦ Two Lane repair
            ◦ Single Lane repair with Lane reversal
                ◦ x64 Advanced Package Pseudo Codes
                ◦ x32 Advanced Package Pseudo Codes
            ◦ Two Lane repair with Lane reversal
                ◦ x64 Advanced Package Pseudo Codes
                ◦ x32 Advanced Package Pseudo Codes
            ◦ Clock and Track Lane remapping
            ◦ Clock and Track Lane repair implementation
            ◦ Valid Repair and implementation
            ◦ Width Degrade in Standard Package Interfaces
        ◦ Data to Clock Training and Test Modes
            ◦ Scrambling and training pattern generation
        ◦ Link Initialization and Training
            ◦ Link Training Basic Operations
                ◦ Transmitter initiated Data to Clock Point Test
                ◦ Transmitter initiated Data to Clock Eye Width Sweep
                ◦ Receiver initiated Data to Clock point test
                ◦ Receiver initiated Data to Clock Eye Width Sweep
            ◦ Link Training with Retimer
            ◦ Link Training State Machine
                ◦ RESET
                ◦ Sideband Initialization (SBINIT)
                ◦ MBINIT
                ◦ MBTRAIN
                ◦ LINKINIT
                ◦ ACTIVE
                ◦ PHYRETRAIN
                ◦ TRAINERROR
                ◦ L1/L2
            ◦ Runtime Recalibration
            ◦ Multi-module Link
                ◦ Multi-module initialization
                    ◦ Sideband Assignment and Retimer Credits for Multi-module configurations
                    ◦ Examples of MMPL Synchronization
                ◦ Multi-module Interoperability between x64 and x32 Advanced Packages
            ◦ Sideband PHY Arbitration between MPMs and Link Management Packets

• Introduction
• UCIe-3D Features and Summary
• UCIe-3D Tx, Rx, and Clocking
• Electrical Specification
    ◦ Timing Budget
    ◦ ESD and Energy Efficiency
    ◦ UCIe-3D Module and Bump Map
    ◦ Repair Strategy
    ◦ Channel and Data Rate Extension

• Protocol Specification
    ◦ Packet Types
    ◦ Packet Formats
        ◦ Register Access Packets
        ◦ Messages without Data
        ◦ Messages with data payloads
        ◦ Management Port Message (MPM) with Data
        ◦ MPMs without Data
    ◦ Flow Control and Data Integrity
        ◦ Flow Control and Data Integrity over FDI and RDI
        ◦ Flow Control and Data Integrity over UCIe sideband Link between dies
        ◦ End-to-End flow control and forward progress for UCIe Link sideband Operation on RDI and FDI

• UCIe Manageability
    ◦ Overview
    ◦ Theory of Operation
    ◦ UCIe Management Transport
        ◦ UCIe Management Transport Packet
            ◦ Traffic Class and Packet Ordering Requirements
            ◦ Packet Length
            ◦ Management Protocol
        ◦ Management Network ID
        ◦ Routing
            ◦ Routing of a Packet from a Management Entity within the Chiplet
            ◦ Routing of a Packet Received on a Management Port
        ◦ Packet Integrity Protection
            ◦ CRC Integrity Protection
        ◦ Access Control
            ◦ Standard Asset Classes
            ◦ Security Director
        ◦ Initialization and Configuration
            ◦ Management Capability Directory
            ◦ Chiplet Capability Structure
            ◦ Access Control Capability Structure
            ◦ Security Clearance Group Capability Structure
        ◦ UCIe Memory Access Protocol
            ◦ UCIe Memory Access Protocol Packets
                ◦ UCIe Memory Request Packet
                ◦ UCIe Memory Access Response Packet
            ◦ UCIe Memory Access Protocol Capability Structure
        ◦ Management Transport Packet (MTP) Encapsulation
            ◦ MTP Encapsulation Architecture Overview
            ◦ Management Port Messages
                ◦ Sideband
                ◦ Mainband
                    ◦ MPMs with Data
                    ◦ MPMs without Data
            ◦ Management Transport Path Setup
                ◦ Sideband
                    ◦ Negotiation Phase Steps
                    ◦ Initialization Phase Steps
                    ◦ Other Sideband Management Transport Path Rules
                ◦ Mainband
                    ◦ Negotiation Phase Steps
                    ◦ Initialization Phase Steps
                    ◦ Other Mainband Management Transport Path Rules
                ◦ Common Rules for Management Transport over Sideband and Mainband
                    ◦ Management Packet Flow Control
                    ◦ Segmentation
                    ◦ Interleaving and Multi-module Sideband and Multi-stack Mainband Ordering
                        ◦ Transmitter Rules
                        ◦ Receiver Rules
                    ◦ ‘Init Done’ Timeout Flow
            ◦ Other Management Transport Details
                ◦ Sideband
                    ◦ Management Port Gateway Flow Control over RDI
                    ◦ MPMs with Data Length Rules
                    ◦ Sideband Runtime Management Transport Path Monitoring — Heartbeat Mechanism
                    ◦ Sideband Management Path Power Management Rules
                    ◦ Management Port Gateway Mux Arbitration
                ◦ Mainband
                    ◦ NOP Message
                    ◦ Credit Return DWORD Format
                    ◦ Management Flit Formats
                    ◦ L1/L2 Link States and Management Transport
                    ◦ Link Reset/Link Disable and Management Transport
                ◦ Retimers and Management Transport
    ◦ UCIe Debug and Test Architecture (UDA)
        ◦ Overview
            ◦ DFx Management Hub (DMH)
            ◦ DFx Management Spoke (DMS)
            ◦ Supported Protocols
                ◦ UCIe Memory Access Protocol (UMAP)
                ◦ Vendor-defined Test and Debug Protocol
            ◦ UDM and UCIe Memory Access Protocol Message Encapsulation over UCIe
            ◦ UCIe Test Port Options and Other Considerations
                ◦ Determinism Considerations
            ◦ DFx Security
        ◦ Sort/Pre-bond Chiplet Testing with UDA
        ◦ SiP-level Chiplet Testing with UDA
        ◦ System Debug with UDA
        ◦ DMH/DMS Registers
            ◦ DMH/DMS Register Address Space and Access Mechanism
            ◦ DMH Registers
            ◦ DMS Registers

• High-level Software View of UCIe
• SW Discovery of UCIe Links
• Register Location Details and Access Mechanism
• Software View Examples
• UCIe Registers
    ◦ UCIe Link DVSEC
• UCIe Link Registers in Streaming Mode and System SW/FW Implications
• MSI and MSI-X Capability in Hosts/Switches for UCIe Interrupt
• UCIe Early Discovery Table (UEDT)

• Raw Die-to-Die Interface (RDI)
    ◦ Interface reset requirements
    ◦ Interface clocking requirements
    ◦ Dynamic clock gating
    ◦ Data Transfer
    ◦ RDI State Machine
    ◦ RDI bring up flow
    ◦ RDI PM flow
• Flit-Aware Die-to-Die Interface (FDI)
    ◦ Interface reset requirements
    ◦ Interface clocking requirements
    ◦ Dynamic clock gating
        ◦ Rules and description for lp_wake_req/pl_wake_ack handshake
        ◦ Rules and description for pl_clk_req/lp_clk_ack handshake
    ◦ Data Transfer
        ◦ DLLP transfer rules for 256B Flit Mode
    ◦ Examples of pl_flit_cancel Timing Relationships
    ◦ FDI State Machine
    ◦ Rx_active_req/Sts Handshake
    ◦ FDI Bring up flow
    ◦ FDI PM Flow
• Common rules for FDI and RDI
    ◦ Byte Mapping for FDI and RDI
    ◦ Stallreq/Ack Mechanism
    ◦ State Request and Status
        ◦ Reset State rules
        ◦ Active State rules
        ◦ PM Entry/Exit Rules
        ◦ Retrain State Rules
        ◦ LinkReset State Rules
        ◦ Disabled State Rules
        ◦ LinkError State Rules
        ◦ Common State Rules
    ◦ Example Flow Diagrams
        ◦ LinkReset Entry and Exit
        ◦ LinkError
        ◦ Example of L2 Cross Product with Retrain on RDI
        ◦ L2 Exit Example for RDI