UVM RAL register model training with hands on project

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UVM RAL register model training with hands on project

About Course

UVM register model(RAL) development training is a 21 hours e-learning course focused on all the aspects of register model development, integration, testcase and checker implementation based on register model. USB2.0 core used as reference design for developing register model, integration and testcase development.


Register model training include all the aspects of scripting for register model development, front door access, back door access, testcase development, scoreboard logic etc.

Demo Videos

Unit NumberTopicDuration (Mins)
1Register model overview, Base classes175
2Register model development, integration110
3Ethernet MAC register model development, integration and testcase coding180
4Register write read testcase debug, predict method154
5SPI Master Core Simulation bring up15
6SPI Core TB Overview, Register sequences description62
7Register class methods, simulations149
8Functional coverage in register model154
9Register build-in sequences for register and memory checking74
10Creating tests using build-in sequences112
11USB RAL Model coding62
12Scoreboard implementation for status register checking7
Curriculum

Benefits of eLearning?

 

  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹5,000 + GST

₹5,500    (10% Off)

10 hours left to avail at this price

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