VLSI Training
UVM RAL register model training with hands on project
UVM Register Model (RAL) Development Training is a comprehensive 21-hour e-learning program designed to help engineers and students master the development and integration of the UVM Register…
- 21 HoursCourse Duration
- 12 SessionsRecorded & Live
- 4.6/5Learner Rating
- 700+Enrolled Learners
Course Overview
About Course
UVM Register Model (RAL) Development Training is a comprehensive
21-hour e-learning program designed to help engineers and students
master the development and integration of the UVM Register Abstraction Layer (RAL)
in modern ASIC and SoC verification environments.
This training focuses on the complete workflow of register model development, integration,
testcase creation, and checker implementation using industry-standard
SystemVerilog UVM methodology.
A real-time USB 2.0 controller design is used as the reference RTL
to demonstrate practical implementation of UVM register model development and verification.
The course covers all the critical aspects of UVM RAL modeling including register generation scripting, front-door access, back-door access, register prediction, testcase development, scoreboard implementation, and debugging techniques used in advanced VLSI Design Verification projects. Participants will gain hands-on exposure to industry practices used in ASIC verification and SoC verification environments, enabling them to build scalable and reusable UVM verification components. For more advanced VLSI and Design Verification training programs, visit Inskill Learning Portal.
The course covers all the critical aspects of UVM RAL modeling including register generation scripting, front-door access, back-door access, register prediction, testcase development, scoreboard implementation, and debugging techniques used in advanced VLSI Design Verification projects. Participants will gain hands-on exposure to industry practices used in ASIC verification and SoC verification environments, enabling them to build scalable and reusable UVM verification components. For more advanced VLSI and Design Verification training programs, visit Inskill Learning Portal.
Detailed Syllabus
4 modulesSession-wise Content
12 sessions · 20h 54m- 1Register model overview, Base classes2h 55m
- 2Register model development, integration1h 50m
- 3Ethernet MAC register model development, integration and testcase coding3h
- 4Register write read testcase debug, predict method2h 34m
- 5SPI Master Core Simulation bring up15m
- 6SPI Core TB Overview, Register sequences description1h 2m
- 7Register class methods, simulations2h 29m
- 8Functional coverage in register model2h 34m
- 9Register build-in sequences for register and memory checking1h 14m
- 10Creating tests using build-in sequences1h 52m
- 11USB RAL Model coding1h 2m
- 12Scoreboard implementation for status register checking7m
Your Instructor
S
Sreenivas Reddy
Founder, VLSIGuru
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
What Our Students Say
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- No per-requisites. Good to know C language & exposure to Digital Design concepts
- Each aspect of course is supported by lot of practical examples
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts