Verilog for Design and Verification

VERILOG FOR DESIGN AND VERIFICATION

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Verilog for Design and Verification

About Course

Verilog for Design & Verification (VG-VERILOG) is a 46 hours of theory and 30 hours of labs course with detailed emphasis on Verilog for complex design implementation and verification. VT-VERILOG course is targeted for both design & verification engineers to gain expertise in Verilog for design & testbench development. This is must do course for every electronics and electrical graduate. Student may also opt for course on advanced digital design and basic analog design conceptsAdvanced Digital Design Training.

Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for the same, and all these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG

Verilog language constructs with detailed examples on each construct usage
Multiple Design Coding & Testbench development
Access to Questasim tool
Hands on labs & Hands on projects

Unit Number	Topic	Duration(Mins)
1	overview of verilog language	4
2	gvim for verilog coding	44
3	Verilog language evolution	36
4	verilog language evolution	29
5	implementing combinational logic using verilog	61
6	implementing combinational logic using verilog	59
7	implementing combinational logic using verilog	86
8	introduction to verilog language constructs	79
9	introduction to verilog language constructs	77
10	introduction to verilog language constructs	31
11	encoders continue	47
12	encoders continue	16
13	demux concepts	12
14	Verilog language litrels(vector,integer,real,datatypes)	31
15	verilog language litrels(vector,integer,real,datatypes)continue	77
16	Verilog Language	75
17	vector assignments	82
18	vector assignments(continue)	28
19	datatypes	53
20	arrays	93
21	arrays	92
22	arrays(continue)	51
23	sting and event	26
24	unique array	45
25	heirarical modeling	30
26	heirarical modeling(continue)	86
27	heirarical modeling(continue)	15
28	task and functions	73
29	task and functions(continue)	52
30	operators	30
31	operators(continue)	92
32	operators(continue)	44
33	verilog code(execution styles) (fork join)	28
34	dataflow modeling	9
35	structural modeling	21
36	behavioral style of coding	58
37	behavioral style of coding continue	43
38	Blocking and non blocking	76
39	synthesis examples	7
40	synthesis examples(continue)	6
41	procedural statements	45
42	casez and casez	23
43	timescale	10
44	prime number logic	16
45	timescale(continue)	21
46	inter delay and intra delay	23
47	system task and system function	24
48	system task and system function(continue)	66
49	complier directives	7
50	complier directives(continue)	85
51	FSM	67
52	Pattern detector	40
53	APB	37
54	Synchronous FIFO SES1	54
55	Synchronous FIFO SES2	68
56	Asynchronous FIFO SES1	12
57	Asynchronous FIFO SES2	85
58	Asynchronous FIFO SES3	34
59	Interrupt Controller SES1	78
60	Interrupt Controller SES2	120
61	PISO SES1	90
62	PISO SES2	93
63	SPI Controller - Register programming	100
64	SPI Controller - Write transaction implementation	70
65	Dual Port RAM	5
66	CRC calculation	29
67	CRC	30
68	SPI Read transaction implementation	47

Curriculum

1 : Verilog Language Constructs

How Verilog differs from other programming languages?

Verilog language concepts

Registers, nets

Vectors, Array

Memories

Data types

Operators

Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level

Procedural Blocks

Continuous assignments

Procedural Statements

Generate

State Machines

Gate Level Implementation

Hierarchical modeling

Verilog Programming Interface(& PLI)

Pipelining

FSM : Mealy and Moore

FSM State encoding styles

2 : Verilog hands on design and verification projects

Flipflop (Synchronous & Asynch Reset), Latch

Counter-Gray code counter, modulo, ring, johnson, up counter, down counter

Shift register implementation

Half adder, full adder, multiplexer

Dual port memory write, read design & testbench

encoder, decoder, various gates

Primitive implementation using table, endtable

Pattern detector

Coin counter for tea vending machine

Traffic light controller(TLC)

CRC generation code

Watchdog timer implementation

Synchronous FIFO

Asynchronous FIFO

Memory implementation

example to showcase race condition using blocking assignments

system task usage: $display, $monitor, $strobe

PLI, VPI implementation

Memory controller RTL understanding, architecture understanding

Clock generation with Duty cycle & Jitter

Interrupt Controller

SPI Controller

I2C Controller

UART Controller

Benefits of eLearning?

Access to the Instructor - Ask questions to the Instructor who taught the course
Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

Course Instructor

SRINIVAS REDDY

Founder, VLSIGuru Institute
Dual Degree(VLSI Design), IIT Madras
14 years of industry experience

Price - ₹12,000 + GST

₹14,250 (15% Off)

10 hours left to avail at this price

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TESTIMONIALS

What Our Students Says About Inskill

Tom Jones

Tesla CMO

Uday G R

VLSIGURU training institute is one of the best training institute for VLSI domain.
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10.04.2018

Nishu Nisarga G.S

Functional verification engineer

Nishu Nisarga G.S

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5 Month Ago

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Doctor

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