verilog For Design & language

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verilog For Design & language

About Course

Verilog for Design & Verification (VG-VERILOG) is a 23 hours of theory and 30 hours of labs course with detailed emphasis on Verilog for complex design implementation and verification. VT-VERILOG course is targeted for both design & verification engineers to gain expertise in Verilog for design & testbench development. This is must do course for every electronics and electrical graduate. Student may also opt for course on advanced digital design and basic analog design conceptsAdvanced Digital Design Training.

Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for the same, and all these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG

Unit NumberTopicDuration(Mins)
1overview of verilog language4
2gvim for verilog coding44
3Verilog language evolution36
4verilog language evolution29
5implementing combinational logic using verilog61
6implementing combinational logic using verilog59
7implementing combinational logic using verilog86
8introduction to verilog language constructs79
9introduction to verilog language constructs77
10introduction to verilog language constructs31
11encoders continue47
12encoders continue16
13demux concepts12
14Verilog language litrels(vector,integer,real,datatypes)31
15verilog language litrels(vector,integer,real,datatypes)continue77
16Verilog Language75
17vector assignments82
18vector assignments(continue)28
19datatypes53
20arrays93
21arrays92
22arrays(continue)51
23sting and event26
24unique array45
25heirarical modeling30
26heirarical modeling(continue)86
27heirarical modeling(continue)15
28task and functions73
29task and functions(continue)52
30operators30
31operators(continue)92
32operators(continue)44
33verilog code(execution styles) (fork join)28
34dataflow modeling9
35structural modeling21
36behavioral style of coding58
37behavioral style of coding continue43
38Blocking and non blocking76
39synthesis examples7
40synthesis examples(continue)6
41procedural statements45
42casez and casez23
43timescale10
44prime number logic16
45timescale(continue)21
46inter delay and intra delay23
47system task and system function24
48system task and system function(continue)66
49complier directives7
50complier directives(continue)85
Curriculum

How Verilog differs from other programming languages?
Verilog language concepts
Registers, nets
Vectors, Array
Memories
Data types
Operators
Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
Procedural Blocks
Continuous assignments
Procedural Statements
Generate
State Machines
Gate Level Implementation
Hierarchical modeling
Verilog Programming Interface(& PLI)
Pipelining
FSM : Mealy and Moore
FSM State encoding styles
Flipflop (Synchronous & Asynch Reset), Latch
Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
Shift register implementation
Half adder, full adder, multiplexer

Benefits of eLearning?

 

  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹6,000 + GST

₹7000/    (10% Off)

10 hours left to avail at this price

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