- Classes : Object Oriented Programming
- Arrays, Data Types, Literals, Operators
- Scheduling Semantics, Inter process Synchronization
- Processes, Threads, Tasks and Functions
- Randomisation, Constraints
- Interface, Clocking blocks, Program Block
- Functional Coverage
- Assertion Based Verification
- System Tasks & Functions
- Compiler Directives
- DPI
- AXI4.0 : Features, Signals, Timing Diagrams
- AXI VIP Architecture Development
- VIP Component Coding
- AXI Slave model test case development
- Test Case debugging
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
- Specification analysis
- Verification Plan creation
- Feature & Scenario Listing down
- TB architecture creation
- Building Top level verification environment
- TB component coding and integration
- Sanity test case and environment bring up
- Complete test case coding
- Building regression test suite
- Functional coverage and code coverage analysis
- What is UVM?
- Need for Methodology?
- UVM Overview
- OOPs Basics
- UVM TB Architecture
- Phasing
- UVM Base classes
- Simple UVM Test Example
- UVM Command line processor
- Reporting classes
- Factory
- Config DB, Resource DB
- TLM 1.0
- Sequence, Sequencer
- Monitor and Scoreboard Basics
- Virtual Sequencer
- AHB Protocol
- AHB UVC Development
- Monitor and Scoreboard
- Sequence library
- TLM2.0
- Synchronization classes
- Event, Barrier
- Policy classes
- Printer, comparator
- Packer, Recorder
- Pools
- Phase jumping
- Register Layer classes
- Callbacks
- Comparator
- Heartbeat
- Report catcher
- Register Layer development for USB2.0 core
- AHB Interconnect model functional verification
₹37000