Functional Verification Training for Experienced Engineers

Unit Number	Topic	Duration (Mins)
1	Course overview, prerequisites, assignments	45
2	Functional verification overview	15
3	Driving factors of verification, why SV?	12
4	TB development : modularity, reusability	63
5	SV Training objectives	5
6	Running SV code with Questasim	3
7	SV language concepts	49
8	SV language concepts	42
9	Array basics	37
10	Verilog language shortcomings	14
11	SV language features	27
12	Literals	30
13	Data types: Integer based	47
14	String data type	77
15	Arrays	17
16	Packed and unpacked arrays	43
17	Multi dimensional arrays	53
18	Dynamic arrays	61
19	Associative arrays basics	14
20	Associative array methods	95
21	Queues	53
22	Operators	36
23	Operators	92
24	Operators	53
25	Operator overloading	14
26	Object oriented programming basics	21
27	APB Tx class definition	90
28	APB tx class methods	84
29	Ethernet frame definition, Inheritance	108
30	Ethernet frame methods, static, rand, randc,	93
31	Pack, unpack, array of packets	48
32	Properties, variable scope	69
33	New	27
34	Class randomize methods	78
35	User defined methods	34
36	Encapsulation	46
37	Polymorphism	89
38	Polymorphism example	81
39	This, super	16
40	OOP summary	30
41	parameterized classes	118
42	Static methods and properties	19
43	Interface class	12
44	Constant class property	8
45	Scope resolution operator	60
46	Copy, $cast	98
47	$cast	35
48	Data types: CHandle	38
49	User defined data types	31
50	Struct	90
51	Revision, rand, pattern 0->1->0->1 generation	29
52	Union	12
53	Enum	32
54	Labeling	2
55	IPS	19
56	Doubt clarification : medal array	10
57	Inter process synchronization	74
58	Event	43
59	Semaphore	68
60	Memory testbench setup and interface instantiation	85
61	Functional coverage in Memory TB	98
62	CLocking block	98
63	Interface	79
64	SPI Interface coding	6
65	Memory TB with semaphore	22
66	Memory TB with configurable number of agents	110
67	Debugging null issue	38
68	Scoreboarding logic	57
69	Fork, join	57
70	Scheduling scemantics	10
71	Program	13
72	Debug session	2
73	Task, functions	42
74	System task, functions	13
75	Constraints and randomization	27
76	Constraints types	92
77	Constraints virtual nature, randcase, constraint types	59
78	Inline and Implication constraints example	14
79	Constraints writing examples - interview focused	57
80	Constraints example for multi chip select design	40
81	Functional coverage introduction	88
82	Functional coverage: covergroups, bins, cross coverage	63
83	Functional coverage - Instance coverage	10
84	FIFO Functional coverage	10
85	Coverage intersect	60
86	Coverage option	26
87	Coverage options, transition coverage	40
88	Coverage system tasks	2
89	Code coverage	10
90	Coverage analysis	34
91	Code coverage analysis using coverage report	68
92	SV Conditional coverage unmasking condition	11
93	Assertions: Introduction, types, examples, sequences, properties, ## operator,	162
94	Assertion examples	76
95	Assertion debug and analysis	12
96	Listing down assertions for Interrupt controller	8
97	DPI, Compiler directives, VCD, Libraries	107
98	SV Package significance	3
99	Common array methods, conversion methods, Callbacks detailed explanation	148
100	Ethernet Loopback Design	98
101	SYSTEM VERILOG
102	UVM TB Simulation on EDA PLAYGROUND	19
103	Agenda, course schedule	11
104	What is UVM	17
105	Need for methodology	43
106	UVM overview, OOP basics	27
107	UVM TB architecture	14
108	Factory basics	12
109	UVM TB example	49
110	Memory TB development	95
111	Memory TB development : Coverage, Monitor	87
112	Memory TB development : Testcase coding	137
113	UVM Questions	61
114	Doubts, Sequence layering	70
115	UVM Root	31
116	UVM Objection basics	9
117	revision, UVM base classes	30
118	Command line processor (uvm_cmdline_processor)	21
119	Doubt Clarification	3
120	UVM TB example contd, Objections	149
121	revision, Question-answers	55
122	reporting classes	58
123	UVM common phases	30
124	UVM command phases - Question & answers	16
125	Factory (uvm_factory)	19
126	Revision	62
127	UVM scheduled phases - run sub phases	3
128	Factory, TB Development	89
129	UVM config DB	80
130	question - answers and revision	16
131	configuration database (config_db)	50
132	resource db	108
133	TLM Basics, TLM Push model	48
134	revision, questions, config_db	24
135	TLM - Pull, FIFO and Broadcast model	83
136	TLM TB connection types	22
137	TLM Connection assignment solution	61
138	Driver - Sqr communication	17
139	Test library, Sequnece library, Sequence-Sequencer relation	84
140	default_sequence in UVM sequencer	23
141	sequence, virtual sequencer	32
142	Virtual sequencer and virtual sequences	111
143	UVM doubt clarification	46
144	Asynchronous FIFO UVM TB Development	107
145	Asynchronous FIFO TB : Scoreboard development, virtual sequencer	80
146	UVM ESSENTIALS
147	AXI Protocol introduction	206
148	AXI Protocol features	109
149	AXI Protocol advanced features	103
150	AXI Protocol advanced features	65
151	VIP development concepts, VIP template coding	45
152	VIP BFM and Generator coding, Testcase development	97
153	VIP monitor and coverage coding, Coverage report analysis	161
154	Reference model and checker coding,	161
155	Assertions coding, Advanced feature implementation	83
156	AXI advanced feature implementation, Slave implementation as a slave VIP	60
157	Advanced feature checking	25
158	AXI UVC Development	68
159	AXI Scoreboard coding - 2 different styles	183
160	AXI Scoreboard integration steps	6
161	AXI, AHB interview questions	4
162	AXI Interconnect development concepts	6
163	AXI WRAP FIXED Burst Implementation concepts	52
164	AXI VIP
165	Protocol overview	109
166	Protocol advanced concepts	153
167	Ethernet MAC design specification understanding	105
168	Register field description	93
169	Register fields and transmit, receiver descriptor overview	98
170	Feature list down, testplan development	124
171	Understanding DMA descriptors using AXI protocol	44
172	testplan development, functional coverage listing down, TB architecture development	108
173	Testbench development lab session	130
174	TB development and cleanup	90
175	TB development lab session	99
176	register access testcase bringup	129
177	register access testcase debug, functional testcase coding	117
178	Lab session	97
179	Register access testcase debug lab session	109
180	Functional testcase bringup	129
181	Lab session	104
182	MAC receive testcase bringup, debug concepts	132
183	Lab session (Clean up required)	125
184	FD Transmit test bringup	80
185	Lab session	104
186	Lab session	107
187	Monitor and register model development	152
188	Part1: Register model and reference model development	107
189	Part2: Lab session	39
190	Reference model, testcase debug, regression setup	138
191	Rx Flow control test case debug	80
192	Collision detection testcase bringup	73
193	Tx and Rx testcase bringup	90
MODULE	ETHERNET MAC

Functional Verification for experienced engineers

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Functional Verification for experienced engineers

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1 : SystemVerilog for Advanced Verification

2 : AXI4.0 protocol and AXI Verification IP Development

3 : ASIC Verification Concepts

4 : Industry Standard Project : DMA Controller Functional Verification

5 : UVM

Functional Verification for experienced engineers

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Functional verification training for experienced

Course Duration : 180 hours theory, 130 hours labs

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