Low-Power Verification with UPF: A Beginner’s Introduction
Modern SoCs rarely operate with a single power supply or a single operating mode. Different blocks may run at different voltages, some blocks may be switched off when they are not required, and important register states may need to be preserved during power-down.
These techniques help reduce power consumption, but they also introduce new verification problems. A design that works correctly when every block is powered on may fail when a domain is switched off, restored, or operated at a different voltage.
This is where low-power verification with UPF becomes important.
The Unified Power Format (UPF), standardized as IEEE 1801, provides a way to describe the power intent of a design separately from its functional RTL. The power intent can then be used across design, verification and implementation flows.
For beginners, the important point is simple:
RTL describes what the design does. UPF describes how the design is powered and what should happen when power conditions change.
This guide explains the fundamentals of UPF-based low-power verification and the concepts a beginner should understand before working on real SoC designs.
What Is Low-Power Verification?
Traditional functional verification primarily checks whether the RTL behaves according to its specification.
For example, a verification environment may check whether:
- A FIFO correctly handles read and write operations
- An AXI interface follows the protocol
- A processor produces the expected result
- A register receives the correct value
- An FSM transitions between states correctly
Low-power verification adds another dimension.
The verification environment must also determine whether the design behaves correctly when:
- A power domain is switched off
- A power domain is switched back on
- Two domains operate at different voltages
- Signals cross between power domains
- Register state needs to be retained
- Isolation needs to be enabled
- Different power states are entered
- Power-management controls change in a particular sequence
Therefore, a low-power design can be functionally correct and still have a power-intent bug.
For example, imagine that a CPU subsystem is powered down while another always-on subsystem continues operating. If signals from the powered-down block are allowed to reach the active block without proper isolation, the receiving logic may see invalid values.
Low-power verification is intended to detect such problems before implementation or silicon.
What Is UPF?
UPF stands for Unified Power Format.
It is used to describe the power intent of a design. IEEE 1801 defines the standard for specifying and working with power intent in energy-aware electronic systems.
The functional RTL might describe a block such as:
CPU → Memory Controller → Peripheral
The UPF description can additionally define:
CPU Domain → Switchable
Memory Domain → Always ON
Peripheral → Different Voltage
It can also describe requirements such as:
- Which blocks belong to each power domain
- Which supply powers a domain
- When a domain can be switched off
- Which signals require isolation
- Which signals require voltage level shifting
- Which registers need state retention
- What power states are legal
UPF therefore complements RTL rather than replacing it.
Why Is UPF Needed for Low-Power Verification?
Consider a simple SoC with two power domains:
+——————+
| Always-On |
| Domain |
+——–+———+
|
Isolation
|
+——–v———+
| Switchable |
| Domain |
+——————+
The switchable domain can be powered down to save leakage power.
When it is ON, it behaves normally.
When it is OFF, however, its outputs cannot simply be treated like normal functional signals.
The verification environment needs to check:
- Was the domain switched off at the correct time?
- Was isolation enabled before the shutdown?
- Were outputs clamped to the expected value?
- Was required state saved?
- Was the state restored correctly?
- Was the domain powered on in the correct sequence?
- Did the design return to functional operation after wake-up?
These are examples of problems that traditional RTL-only simulation may not adequately represent.
Important UPF Concepts Beginners Should Know
Before learning UPF commands, beginners should understand several basic low-power concepts.
1. Power Domains
A power domain is a logical group of design elements that share a particular power supply arrangement.
For example:
PD_TOP
├── CPU
├── Cache
└── Control Logic
PD_PERIPH
├── UART
├── SPI
└── GPIO
The domains may have different power characteristics.
One domain may remain powered continuously while another can be switched off.
In UPF, power domains are part of the power-intent description.
2. Power Supply Network
A low-power design may have multiple supply rails.
For example:
VDD_AON
VDD_CPU
VDD_PERIPH
VSS
The UPF power intent describes the supply architecture and its relationship with power domains.
This becomes important when different blocks operate at different voltages or when a domain can be disconnected from its supply.
3. Isolation Cells
Isolation is one of the most important concepts in low-power verification.
Suppose Domain A can be switched off while Domain B remains active:
Domain A Domain B
Power OFF Power ON
Logic
|
| X / invalid
v
[Isolation]
|
v
Logic
When Domain A is powered down, its outputs may no longer contain valid logic values.
An isolation cell prevents those invalid values from reaching active logic. It can clamp the output to a defined value such as 0 or 1.
Verification therefore needs to check both the isolation strategy and the timing/control of isolation.
For example:
Power Down:
Stop activity
↓
Enable isolation
↓
Switch domain OFF
During wake-up, the sequence needs to be handled correctly as well.
Isolation verification is particularly important because the clamp value and isolation control are part of the interaction between functional behavior and power intent.
4. Level Shifters
Different power domains may operate at different voltage levels.
For example:
CPU Domain : 0.8 V
Always-On Domain : 1.0 V
A signal crossing between these domains may require a level shifter.
Conceptually:
0.8 V Domain
|
| signal
v
[Level Shifter]
|
v
1.0 V Domain
The exact implementation depends on the technology and direction of the voltage crossing.
During low-power verification, engineers need to ensure that the intended crossings are correctly handled.
5. Retention
Powering down a domain normally means that the state stored in ordinary registers can be lost.
But some registers may contain important information that must survive power-down.
A retention strategy is used for such state.
A simplified sequence is:
Before power-down:
SAVE
↓
Register state preserved
↓
Power OFF
↓
Power ON
↓
RESTORE
↓
Original state recovered
Verification must check that the correct state is saved and restored and that the state becomes valid at the expected point in the wake-up sequence.
6. Power States
A complex SoC can operate in several power states.
For example:
Power State | CPU | Peripheral | Description |
ACTIVE | ON | ON | Normal operation |
CPU_SLEEP | OFF | ON | CPU powered down |
LOW_POWER | LOW V | ON | Reduced-voltage operation |
DEEP_SLEEP | OFF | OFF/limited | Maximum power saving |
The allowed combinations can be represented through a Power State Table (PST).
A PST is important because verification needs to know which combinations are legal and what behavior is expected in each state. Accellera’s UPF material describes the power state table as the set of legal combinations of power-domain states.
How Does UPF-Based Verification Work?
A simplified low-power verification flow can be understood in the following steps.
Step 1: Create the RTL
The design is first described using Verilog or SystemVerilog.
For example, the design may contain:
- CPU logic
- Memory controller
- UART
- DMA
- Peripheral blocks
Step 2: Define the Power Architecture
The designer identifies:
- Power domains
- Supply rails
- Switchable blocks
- Always-on blocks
- Voltage differences
- Retention requirements
- Isolation requirements
Step 3: Create the UPF
The power intent is captured using UPF.
A simplified example might look conceptually like:
create_power_domain PD_CPU
create_power_domain PD_AON
# Power intent definitions
# Isolation strategy
# Retention strategy
# Supply definitions
# Power states
The exact UPF syntax and supported commands depend on the UPF version and EDA tool flow, so beginners should learn the concepts before memorizing commands.
Step 4: Run Power-Aware Simulation
The RTL and UPF are loaded into a power-aware simulation environment.
The simulator can then model the effect of the defined power conditions.
Instead of checking only:
Input → RTL → Output
the verification environment can check:
Input
↓
RTL + Power Intent
↓
Power State Transition
↓
Output
Step 5: Verify Power Scenarios
The testbench should exercise different operating conditions.
For example:
ACTIVE
↓
SAVE
↓
ISOLATE
↓
POWER DOWN
↓
POWER UP
↓
RESTORE
↓
ACTIVE
The purpose is to determine whether the design behaves correctly throughout the complete transition.
What Should Be Verified in a UPF Environment?
A beginner should focus on these verification goals.
Power-domain behavior
Check that each domain enters and leaves its intended power states.
Isolation behavior
Check that signals are properly clamped when a source domain is powered down.
Retention behavior
Check that required register values survive power-down and are restored correctly.
Level-shifter behavior
Check that voltage-domain crossings are correctly handled.
Power-state transitions
Check legal transitions between operating modes.
Wake-up behavior
Power-up is just as important as power-down.
The design should return to a valid functional state after restoration.
Control sequencing
The order of events matters.
For example, switching power off before enabling isolation could expose active logic to invalid signals.
Therefore, verification should test not only whether controls eventually reach the correct values, but also whether they occur in the required sequence.
A Simple Example of UPF Verification
Consider a CPU block that can be powered down.
During normal operation:
CPU = ON
Isolation = OFF
Retention = ACTIVE
Before shutdown:
CPU activity stops
↓
State is saved
↓
Isolation enabled
↓
CPU power OFF
During shutdown:
CPU = OFF
Isolation = ON
State = Retained
During wake-up:
CPU power ON
↓
Wait for power stabilization
↓
Restore state
↓
Release isolation
↓
CPU resumes operation
A power-aware test should verify each stage rather than simply checking whether the CPU eventually becomes operational.
What Should a Beginner Learn Before UPF?
UPF is easier to learn if the fundamentals are already clear.
A good learning sequence is:
1. Digital Design
Understand:
- Combinational logic
- Sequential logic
- Flip-flops
- FSMs
- Registers
- Clock and reset
2. Verilog/SystemVerilog
Be comfortable reading and writing RTL.
3. Functional Verification
Understand:
- Testbenches
- Simulation
- Assertions
- Coverage
- Basic UVM concepts
4. Low-Power Concepts
Learn:
- Dynamic power
- Leakage power
- Clock gating
- Power gating
- Multi-voltage design
- Power domains
5. UPF
Then learn:
- Power domains
- Supply networks
- Isolation
- Level shifting
- Retention
- Power states
- Power State Tables
- UPF commands
6. Power-Aware Simulation
Finally, practice complete power-state transitions and debug failures.
This progression is much easier than starting by memorizing UPF syntax.
Final Takeaway
Low-power verification with UPF is about verifying that a design remains functionally correct while its power architecture changes.
The most important concepts for a beginner are:
- Power domains
- Power supplies
- Isolation
- Level shifters
- Retention
- Power states
- Power State Tables
- Power-down and wake-up sequences
- Power-aware simulation
The key idea to remember is:
RTL tells you how the logic behaves. UPF tells you how the power architecture affects that logic.
Once you understand that distinction, UPF becomes much easier to learn.
For VLSI engineers moving toward SoC integration, RTL integration, or verification, learning UPF alongside functional verification provides a useful foundation for understanding modern multi-power-domain designs.