Power Aware(Low power) Verification Training

About Course

Power consumption is significant aspect of increasingly complex SOCs, which are typically used for portable systems. Low power design techniques helps identify the power behavior and minimise the power consumption. Both portable and non-portable systems, requires efficient power management techniques.

This course introduces IEEE 1801 UPF for specifying the idle power management architecture.
... Student will learn SoC power domain architecture , in UPF how to define power intent - supply_port, supply_net, power cells like power switches, isolation cells, level shifters , retention cells, power state table and gating logic. They will also learn how to update a design for the power intent, run the simulation to analyse the power behavior.


Power Management – Need for low power
CMOS basics w.r.t Power Consumption
Low Power Techniques
SoC and PMIC architectures
UPF Concepts
UPF design data flow
UPF Power Intent commands
Memory Controller architecture
Memory Controller low power verification setup
Running low power simulations
How to debug low power issues
Low power assertions and coverage

Course videos

Lecture 1 Low power Session1 2:42:41
Lecture 2 Low powe Session2 2:35:54
Lecture 3 Low power Session3 2:09:04
Lecture 4 Low power Session4 2:00:18

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