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| How Verilog differs from other programming languages? | Verilog language concepts | Registers, nets | Vectors, Array | Memories | Data types | Operators | Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level | Procedural Blocks | Continuous assignments | Procedural Statements | State Machines | Gate Level Implementation | Hierarchical modeling | FSM : Mealy and Moore | FSM State encoding styles |
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| Flipflop (Synchronous & Asynch Reset), Latch |
| Counter-Gray code counter, modulo, ring, johnson, up counter, down counter |
| Shift register implementation |
| Half adder, full adder, multiplexer |
| encoder, decoder, various gates |
| Pattern detector |
| Traffic light controller(TLC) |
| Synchronous FIFO |
| Asynchronous FIFO |
| Memory implementation |
| example to showcase race condition using blocking assignments |
| system task usage: $display, $monitor, $strobe |
| Clock generation with Duty cycle & Jitter |
Course videos
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