Ethernet MAC Functional Verification

About Course

Ethernet MAC Functional Verification training course is a 4 weeks course, focused on Ethernet 10/100Mbps protocol and MAC core verification using System Verilog. Course will cover all aspects of functional verification flow starting from specification, feature list down, testplan, testbench development, testcase coding, regression and coverage analysis. MAC core implemented using DMA, course provides in depth overview of DMA functionality and descriptors.




Curriculum

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Course videos

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Unit 1 Protocol overview 01:48:33
Unit 2 Protocol advanced concepts 02:32:51
Unit 3 Ethernet MAC design specification understanding 01:45:21
Unit 4 Register field description 01:32:12
Unit 5 Register fields and transmit, receiver descriptor overview 01:37:34
Unit 6 Feature list down, testplan development 02:04:06
Unit 7 testplan development, functional coverage listing down, TB architecture development 01:47:37
Unit 8 Testbench development lab session 02:10:16
Unit 9 TB development and cleanup 01:30:26
Unit 10 TB development lab session 01:38:36
Unit 11 register access testcase bringup 02:08:45
Unit 12 register access testcase debug, functional testcase coding 01:56:14
Unit 13 Lab session 01:06:22
Unit 14 Register access testcase debug lab session 01:43:04
Unit 15 Functional testcase bringup 02:09:00
Unit 16 Lab session 01:43:17
Unit 17 MAC receive testcase bringup, debug concepts 02:11:15
Unit 18 Lab session (Clean up required) 02:04:45
Unit 19 FD Transmit test bringup 01:20:23
Unit 20 Lab session 01:46:58
Unit 21 Lab session 01:46:46
Unit 22 Monitor and register model development 02:32:28
Unit 23 Part1: Register model and reference model development 01:46:21
Unit 24 Part2: Lab session 00:38:34
Unit 25 Reference model, testcase debug, regression setup 02:18:06
Unit 26 Rx Flow control test case debug 01:20:03
Unit 27 Collision detection testcase bringup 01:12:37
Unit 28 Tx and Rx testcase bringup 01:29:37


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