PCIe Protocol Training

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PCIe Protocol Training

Course Duration : 6 weeks

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About Course

All high speed protocols like USB3, PCIe, SATA, UFS, etc are all based on OSI architecture. Course focus on teaching all the required concepts of different layers in PCIe.


... Course also cover design & testbench implmentation for transaction, Data link and physical layers of PCIe.

Curriculum

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PCIe Background
PCIe Architecture Overview
Configuration Overview
Address Space and Transaction Routing
Transaction Layer:
TLP types and fields
Flow Control
Quality of Service
VC, TC and Transaction Ordering
Data Link Layer:
DLLP types and fields
Flow control
Ack/Nak protocol
Physical Layer:
Physical layer Logical for Gen1, Gen2, and Gen3
Physical layer Electrical for Gen1, Gen2, and Gen3
Link Initialization and Training
Additional PCIe topics
Interrupt support
Error detection and handling
Power management
System Reset

Course videos

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Unit 1 PCIe training overview and training agenda 00:03:54
Unit 2 PCIe Protocol overview 00:50:33
Unit 3 How PCIe evolved 00:26:34
Unit 4 How PCIe differs from PCI 00:11:24
Unit 5 parallel protocols drawbacks 00:05:34
Unit 6 Enumeration: PCIe device Address range mapping 01:03:54
Unit 7 PCI configuration space 00:11:37
Unit 8 Introduction to PCIe topology 00:34:24
Unit 9 PCie device layers 00:15:26
Unit 10 PCIe revision 00:14:17
Unit 11 PCIe Transaction flow example 01:35:57
Unit 12 part1-Enumeration 00:30:49
Unit 13 Revision Transaction flow example and enumeration 00:14:19
Unit 14 PCIe configuration header 00:37:20
Unit 15 BAR 00:23:44
Unit 16 TLP Routing 00:18:33
Unit 17 TLP types 00:02:39
Unit 18 Revision 00:03:39
Unit 19 Transaction layer features 00:06:53
Unit 20 TLP Header fields 00:40:49
Unit 21 TLP format - Memory transactions 00:40:56
Unit 22 Completion timeouts 00:03:17
Unit 23 Doubts Depracated TLP, PH in TLP 00:07:39
Unit 24 TLP Prefix rules 00:01:47
Unit 25 Transaction ordering, virtual channel, arbitration basics 01:13:26
Unit 26 QOS 00:36:31
Unit 27 Flow control 00:20:34
Unit 28 revision QOS, Flow control 00:18:45
Unit 29 CRCs in various packets, Buffer management in flow control 00:22:02
Unit 30 Flow control 01:09:57
Unit 31 DLL, FCI protocol, DLCMSM 01:05:19
Unit 32 revision(flow control), doubts 00:10:09
Unit 33 DLL revision, DLLPs 00:15:18
Unit 34 Data integrity 00:34:58
Unit 35 Physical layer introduction 01:17:38
Unit 36 Doubts discussion 00:16:04
Unit 37 Ordered sets 01:18:14
Unit 38 LTSSM 00:52:14
Unit 39 Doubts discussion 00:13:47
Unit 40 LTSSM 02:25:56
Unit 41 Doubts discussion 00:09:11
Unit 42 Revision 00:04:05
Unit 43 Interrupt support 00:51:35
Unit 44 Error handling and classification 00:51:10
Unit 45 revision LTSSM, Interrupt, Error handling 00:05:15
Unit 46 power management 00:25:32
Unit 47 Reset mechanism 00:06:33
Unit 48 PIPE 00:36:59
Unit 49 Logic Protocol Analyzers 00:02:52
Unit 50 Gen4 updates 01:05:10
Unit 51 PCIe SOC and IP level verification 00:35:52
Unit 52 PCIe TL functional verification 00:36:15
Unit 53 Assignment-1 discussion 00:19:58
Unit 54 Assignment-3 discussion 00:51:15
Unit 55 Assignment-4 discussion 00:13:10
Unit 56 Assignment-5 discussion 00:28:38
Unit 57 PCIe doubt clarification 01:48:56
Unit 58 PCIe doubt clarification 01:59:16
Unit 59 PCIe doubt clarification 03:25:57


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