UVM Essentials Training with hands on project

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UVM Essentials Training

Course Duration : 4 weeks

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About Course

UVM essentials elearning course (VG-UVMESS) is a 38 hours course offered by Sreenivasa Reddy, Founder, VLSIGuru. Course is targeted for freshers with Systemverilog expertise. Course is structured to enable engineers develop expertise in full breadth of UVM. UVM course is targeted towards engineers looking to explore functional verification techniques involving advanced methodology concepts like factory, databases and register layer. Learning starts from basic examples to complex testbench development coding, to ensure a smooth learning curve.


UVM elearning course is divided in to 2 aspects, initial lectures focused on in depth understanding of language constructs using detailed examples, later part of lectures focused on AHB and APB protocols, UVC development for these protocols. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.


... UVM constructs are learnt using more than 100+ detailed examples covering all aspects of UVM starting from base clases, uvm_root, messaging classes, policy classes, factory, configuration, resource data bases, TLM1.0, TLM2.0, sequences, sequence libraries, layered sequences, virtual sequences and sequencers, event, barrier pools and various advanced concepts like register layer, etc. AHB Interconnect design is used as a reference example to learn all above aspects of UVM. These examples cover more than 90% of questions asked in VLSI interviews.

Curriculum

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AHB Interconnect verification project used as reference design to learn UVM & OVM
AHB Interconnect will be verified from scratch while teaching all aspects of UVM
UVM/OVM TB Architecture
UVM Root
UVM Class Library, Macros, Utilities
UVM Factory
Config_db, Resource_db
Command line processor
Synchronization classes
UVM Components, Comparators
Sequences, Sequencers
virtual sequencer and sequences
Creating UVCs and Environment
Simulation Phases
Scheduled phases
TLM1.0
Push
Pull
FIFO
Analysis
Configuring TB Environment
Objections
Configuration DB & Resource DB
Creating TB infrastructure
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AHB Protocol
AHB System architecture
Features
Signals
Timing Diagrams
AHB UVC Architecture
AHB UVC Component Coding
AHB UVC Sequence & Test Development
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AHB Interconnect Testbench Architecture
AHB UVC & APB UVC in Interconnect Testbench setup
VIP Component Coding
Verification Component Coding
Testcase & virtual sequence Development & Debug

Course videos

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Unit 1 Agenda, course schedule 00:11:01
Unit 2 What is UVM 00:17:05
Unit 3 Need for methodology 00:42:45
Unit 4 UVM overview, OOP basics 00:26:38
Unit 5 UVM TB architecture 00:13:29
Unit 6 Factory basics 00:11:44
Unit 7 UVM TB example 00:48:13
Unit 8 Memory TB development 01:54:56
Unit 9 Memory TB development : Coverage, Monitor 01:27:08
Unit 10 Memory TB development : Testcase coding 02:16:19
Unit 11 UVM Questions 01:00:23
Unit 12 Doubts, Sequence layering 01:09:29
Unit 13 UVM Root 00:30:52
Unit 14 objection basics? 00:08:23
Unit 15 revision, UVM base classes 00:30:02
Unit 16 Command line processor: 00:20:40
Unit 17 Student Doubt Clarification 00:02:44
Unit 18 UVM TB example contd, Objections 02:28:20
Unit 19 revision, Question-answers 00:54:32
Unit 20 reporting classes 00:57:25
Unit 21 UVM phases 00:29:38
Unit 22 Factory: 00:19:02
Unit 23 revision: 01:01:54
Unit 24 scheduled UVM phases 00:02:11
Unit 25 Factory, TB Development 01:27:30
Unit 26 UVM config DB 01:19:53
Unit 27 questions, revision 00:15:15
Unit 28 config_db 00:49:34
Unit 29 resource db 01:48:15
Unit 30 TLM1.0 00:47:40
Unit 31 revision, questions, config_db 00:23:48
Unit 32 TLM1.0 01:27:10
Unit 33 Driver - Sqr communication 00:05:20
Unit 34 Test library, Sequnece library, Sequence-Sequencer relation 01:23:39
Unit 35 sequence, virtual sequencer 00:31:19
Unit 36 AHB protocol: Round robin priority, start_item, finish_item: 00:05:55
Unit 37 AHB protocol basics 00:18:22
Unit 38 AHB Basics, AHB system architecture 00:14:45
Unit 39 AHB transfer phases 00:15:31
Unit 40 Handshaking 00:07:05
Unit 41 Arbitration phase 00:13:42
Unit 42 AHB transfer timing diagrams 00:30:37
Unit 43 Signal decoding 00:25:18
Unit 44 AHB transaction example 00:09:12
Unit 45 Burst transfers 00:15:48
Unit 46 AHB features, aligned transfers, wrap transfers 00:58:07
Unit 47 Questions, revision 00:31:22
Unit 48 Features: Address decoding 00:14:39
Unit 49 AHB master signals 00:19:18
Unit 50 AHB features: Early burst termination 00:07:44
Unit 51 Two cycle response 00:07:12
Unit 52 AHB arbitration, Split, retry 00:27:28
Unit 53 Exclusive transfers 00:16:11
Unit 54 AHB UVC: Type of UVC, TB Development using UVC 00:17:32
Unit 55 AHB UVC template development 00:49:36
Unit 56 AHB UVC functional development 00:12:38
Unit 57 revision, questions, AHB transaction coding advanced aspects 00:50:00
Unit 58 AHB Driver coding 01:08:38
Unit 59 AHB Responder coding 00:31:42
Unit 60 AHB monitor coding 00:36:03
Unit 61 AHB interface coding 00:43:18
Unit 62 revision, AHB responder update, AHB UVC issue summary 00:32:40
Unit 63 question 00:07:17
Unit 64 AHB UVC issue debugging 01:52:06
Unit 65 AHB UVC scoreboard 00:32:43
Unit 66 assertions 00:15:28
Unit 67 Implementing testcases 00:30:03
Unit 68 AHB interview questions 00:14:58
Unit 69 revision, AHB interconnect SOC and IP level verification overview 00:05:44
Unit 70 AHB interconnect verification 03:31:48
Unit 71 Sequence library 00:49:26
Unit 72 revision, AHB I/C feature listing down 00:20:10
Unit 73 AHB scoreboard 01:50:00
Unit 74 Virtual sequencer and virtual sequences 01:50:37
Unit 75 UVM-Doubt-clarification 00:46:13
Unit 76 async_fifo_UVM_TB 00:59:08


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