DDR Protocol Training

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DDR Protocol Training

Course Duration : 5 weeks

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About Course

Term DDR in resume opens up quite a few job opportunities!!..that is the importance of DDR in current SoC's..


DDR is an essential component of every complex SOC. It requires every engineer working on SoC to be well versed with DDR protocol concepts including DDR controller, DDR PHY, DDR memory, etc. The course focus on teaching DDR3, DDR4, timing diagrams, training sequence, DDR controller design concepts and DDRPHY concepts.


DDR2, DDR3, DDR4 Training


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DDR memory architecture, pages, banks, rows, columns
DDR bandwidth, transfer rate
DDR Interface signals
DDR commands, timing diagrams
DDR Mode registers
DDR clock frequency, limitation
DDR initialization and power up sequence
DDR Training: Write leveling, Read training, CA Training, ZQ Calibration
DDR use in SoC
LP, PC DDR's
DDR PHY basics
Architecture
Sub components
DDR Controller concepts

Curriculum

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DDR memory architecture, pages, banks, rows, columns
DDR bandwidth, transfer rate
DDR Interface signals
DDR commands, timing diagrams
DDR Mode registers
DDR clock frequency, limitation
DDR initialization and power up sequence
DDR Training: Write leveling, Read training, CA Training, ZQ Calibration
DDR use in SoC
LP, PC DDR's
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LPDDR memory architecture, pages, banks, rows, columns
LPDDR bandwidth, transfer rate
LPDDR Interface signals
LPDDR commands, timing diagrams
LPDDR Mode registers
LPDDR clock frequency, limitation
LPDDR initialization and power up sequence
LPDDR Training: Write leveling, Read training, CA Training, ZQ Calibration
LPDDR use in SoC
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Architecture
Sub components
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Course videos

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Unit 1 DDR technology training agenda 00:07:03
Unit 2 DDR Significance in SOC 00:34:06
Unit 3 SRAM DRAM Cell Basics 00:21:14
Unit 4 DDR Evolution 00:21:014
Unit 5 DDR Wrapper Architecture 00:26:13
Unit 6 DDR frequently used terms, DDR features 03:07:04
Unit 7 DDR system topology - DDR pin description - Burst transfers - Channel, Rank - ECC - LVTTL, SSTL 02:00:50
Unit 8 DDR commands 00:27:01
Unit 9 DDR Operations, Timing diagrams 00:48:38
Unit 10 DDR Signal description 01:19:18
Unit 11 DDR Addressing 00:32:22
Unit 12 Mode registers: DDR1, DDR2 00:26:46
Unit 13 DDR State diagram, Initialization timing diagram 01:30:49
Unit 14 DDR command truth table (DDR2 - DDR4, LPDDR - LPDDR4) 01:05:28
Unit 15 DDR Verilog model simulations 02:23:00
Unit 16 Mode registers: DDR3, DDR4, LPDDR1 to LPDDR4 01:29:43
Unit 17 DLL: Delay locked loop 00:18:53
Unit 18 OCD calibration, ZQ Calibration 00:23:02
Unit 19 Write levelling, Read levelling 00:15:34
Unit 20 ODT : On Die Termination 00:56:18
Unit 21 DDR Refresh: DDR1 to DDR4, LPDDR1 to LPDDR4 01:38:41
Unit 22 DDR3 Feature summary, updates from DDR2 00:36:55
Unit 23 DDR4 features, Feature updates from DDR3 01:12:24
Unit 24 LPDDR Feature Summary: LPDDR1 to LPDDR4 00:06:53
Unit 25 LPDDR1 features 00:10:18
Unit 26 LPDDR2 features 00:34:23
Unit 27 LPDDR3 features 00:15:28
Unit 28 LPDDR4 features 00:57:39
Unit 29 DDR Controller overview 00:36:48
Unit 30 DDR Controller functional verification concepts 00:40:01
Unit 31 DDR PHY Interface (DFI) 01:00:02


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