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DDR memory architecture, pages, banks, rows, columns |
DDR bandwidth, transfer rate |
DDR Interface signals |
DDR commands, timing diagrams |
DDR Mode registers |
DDR clock frequency, limitation |
DDR initialization and power up sequence |
DDR Training: Write leveling, Read training, CA Training, ZQ Calibration |
DDR use in SoC |
LP, PC DDR's |
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LPDDR memory architecture, pages, banks, rows, columns |
LPDDR bandwidth, transfer rate |
LPDDR Interface signals |
LPDDR commands, timing diagrams |
LPDDR Mode registers |
LPDDR clock frequency, limitation |
LPDDR initialization and power up sequence |
LPDDR Training: Write leveling, Read training, CA Training, ZQ Calibration |
LPDDR use in SoC |
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Architecture |
Sub components |
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Course videos
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Lecture 1 | DDR Session1 | 1:45:03 | |
Lecture 2 | DDR Session2 | 03:07:04 | |
Lecture 3 | DDR Session3 | 02:01:42 | |
Lecture 4 | DDR Session4 | 01:50:53 | |
Lecture 5 | DDR Session5 | 01:47:13 | |
Lecture 6 | DDR Session6 | 02:22:54 | |
Lecture 7 | DDR Session7 | 01:47:04 | |
Lecture 8 | DDR Session8 | 01:38:02 | |
Lecture 9 | DDR Session9 | 01:41:49 | |
Lecture 10 | DDR Session10 | 01:11:44 | |
Lecture 11 | DDR Session11 | 01:20:05 | |
Lecture 12 | DDR Session12 | 02:06:02 | |
Lecture 13 | DDR Session13 | 01:08:30 | |
Lecture 14 | DDR Session14 | 55:02 |
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