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| Introduction |
| Protocol overview |
| UART architecture |
| Signal Descriptions |
| UART transactions |
| Write |
| Read |
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| UVC architecture |
| UVC components |
| UVC types |
| Master, Slave |
| Active, Passive |
| UVC test scenario listing down |
| UVC component coding |
| Driver, Sequencer, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
Course videos
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| Lecture 1 | UART Protocol training | 03:00:15 | |
| Lecture 2 | UART UVC Development | 02:47:01 | |
| Lecture 3 | UART Scoreboard and checker development | 02:00:16 | |
| Lecture 4 | UART sequence and testcase coding | 02:00:16 |
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