PCIe Transaction Layer UVC development training

PCIe Transaction Layer UVC Development Training

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₹7000

PCIe TL UVC Development training

Course Duration : 5 weeks

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About Course

PCIe Transaction layer UVC development is focused on developing UVC components for PCIe AXI and TL-DLL interface. These UVC are integrated with TL RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding. Sessions also focused on developing the sequences for AXI and TL-DLL interfaces, using these sequences to create the testcases. Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.

Trainer Exp

15 Years

Tool Access

Yes

Complete Course Material

Yes

Curriculum

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1 : PCIe TL basics

Introduction

Protocol overview

Features

Scenarios

Verification plan

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2 : PCIe TL UVC

Transaction layer RTL coding

TL Testbench architecture, testplan development

UVC architecture and components

UVC component coding

AXI UVC, TL-DLL UVC

Testbench component integration

UVC sequence coding for AXI and DLL interface

Testcase coding

Testcase run and waveform analysis

Testbench integration

Simulations and waveform analysis

Functional coverage analysis

Course videos

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View all the course videos

Unit 1	PCIe TL DV SES1	01:08:18
Unit 2	PCIe TL DV SES2	01:17:15
Unit 3	PCIe TL DV SES3	01:31:20
Unit 4	PCIe TL DV SES4	01:27:51
Unit 5	PCIe DV TL Ses5	01:08:48
Unit 6	PCIe DV TL Ses6	01:20:18
Unit 7	PCIe DV TL Ses7	01:02:46
Unit 8	PCIe DV TL Ses8	01:02:46
Unit 9	PCIe DV TL Ses8	01:32:39
Unit 10	PCIe DV TL Ses9	01:12:06
Unit 11	PCIe DV TL Ses10	01:13:06
Unit 12	PCIe DV TL Ses11	01:12:43

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