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| Introduction |
| Protocol overview |
| SPI architecture |
| Signal Descriptions |
| SPI transactions |
| Write |
| Read |
| Multiple slaves |
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| UVC architecture |
| UVC components |
| UVC types |
| Master, Slave |
| Active, Passive |
| UVC test scenario listing down |
| UVC component coding |
| Driver, Sequencer, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
Course videos
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| Unit 1 | SPI PROTOCOL, SPI Controller RTL, SPI verification using Verilog | 02:58:00 | |
| Unit 2 | SPI UVC Development | 02:15:40 |
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