Universal Memory Controller Functional Verification

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Universal Memory Controller functional verification

Course Duration : 5 weeks

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About Course

Universal Memory controller design support various types of memories like SRAM, SDRAM, Flash, ROM and Synchronous memory devices. It supports 8 chip selects with configurable memory sizes and timing behavior. This project provides student with detailed exposure to complete project flow starting from reading the specification till coverage report generation and regression analysis


... Student will get exposure to regression setup, coverage analysis and scoreboard development. This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow..


Curriculum

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Reading design specification
Understanding design architecture, sub blocks, register definitions, interfaces
Listing down features, scenarios
Develop testplan
Functional coverage point list down
Develop Testbench architecture
Testbench component coding and integration
Skeletal TB structure coding
Functional coding
Develop sanity testcases(smoke testcases)
Bringup testbench environment using sanity testcases
Develop rest of testbench components
Develop functional testcases
Setup regression using Python script
Verification closure
Debug regression failures
Functional, Code and assertion coverage analysis

Course videos

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Lecture 1 MEM_CTRL Session1 03:07:36
Lecture 2 MEM_CTRL Session2 02:31:41
Lecture 3 MEM_CTRL Session3 02:53:07
Lecture 4 MEM_CTRL Session4 03:19:14
Lecture 5 MEM_CTRL Session5 02:18:45
Lecture 6 MEM_CTRL Session6 03:02:05
Lecture 7 MEM_CTRL Session7 03:10:20
Lecture 8 MEM_CTRL Session8 01:44:23


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