PCIe Physical Layer UVC development training

PCIe Physical Layer UVC Development Training

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₹7000

PCIe PL UVC Development training

Course Duration : 5 weeks

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About Course

PCIe Physical layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and PL-PHY interface. These UVC are integrated with Physical Layer RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding. Sessions also focused on developing the sequences for AXI, TL-DLL and PL-PHY interfaces, using these sequences to create the testcases. Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.

Trainer Exp

15 Years

Tool Access

Yes

Complete Course Material

Yes

Curriculum

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1 : PCIe Physical layer basics

Introduction

Protocol overview

Features

Scenarios

Verification plan

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2 : PCIe Physical layer UVC

Physical layer RTL coding

Physical layer Testbench architecture, testplan development

UVC architecture and components

UVC component coding

AXI UVC, DLL-TL and PL-PHY UVC

Testbench component integration

UVC sequence coding for AXI, TL and PHY interface

Testcase coding

Testcase run and waveform analysis

Testbench integration

Simulations and waveform analysis

Functional coverage analysis

Course videos

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View all the course videos

Lecture 1	PHYSICAL LAYER OVERVIEW, PL INTERFACE, TEMPLATE RTL AND TB CODING	01:13:44
Lecture 2	PCIe PL SES2 TB component template coding.	48:53
Lecture 3	PCIE PL SES3 LTSSM Detect to Polling..	34:29
Lecture 4	PCIe PL SES4 RTL coding	02:00:16
Lecture 5	PCIe PL SES5 Polling active TS1 transmit	01:04:52
Lecture 6	PCIe PL SES6 Polling active TS1 TS2 handshake till Configuration_state	46:09
Lecture 7	PCIe PL SES7 Update from Single lane link to multi lane link	28:25
Lecture 8	PCIe PL SES8 Configuration Link Width Start to accept State	56:27

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