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| Fundamental VHDL units |
| Library Declaration |
| Entity Declaration |
| Architecture Declaration |
| Data types |
| Basic TextIO |
| Primitive programming |
| Data flow programing |
| Signals & Variables, State machines |
| Memory Designing |
| Structural programming |
| Function & Procedure |
| Hierarchical Designs |
| Parameterized Design entities |
| Procedural Testbenches |
| Labs based on simple design examples like FIFO, Dual port RAM, FSM’s, etc |
Course videos
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| Lecture 1 | VHDL Session1 | 1:33:08 | |
| Lecture 2 | VHDL Session2 | 3:59:59 | |
| Lecture 3 | VHDL Session3 | 3:10:15 | |
| Lecture 4 | VHDL Session4 | 50:52 | |
| Lecture 5 | VHDL Session5 | 3:22:23 | |
| Lecture 6 | VHDL Session6 | 1:00:16 |
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