Power Aware(Low power) Verification Training

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Power Aware(Low power) verification

Course Duration : 3 weeks

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About Course

Power consumption is significant aspect of increasingly complex SOCs, which are typically used for portable systems. Low power design techniques helps identify the power behavior and minimise the power consumption. Both portable and non-portable systems, requires efficient power management techniques.


This course introduces IEEE 1801 UPF for specifying the idle power management architecture.
... Student will learn SoC power domain architecture , in UPF how to define power intent - supply_port, supply_net, power cells like power switches, isolation cells, level shifters , retention cells, power state table and gating logic. They will also learn how to update a design for the power intent, run the simulation to analyse the power behavior.

Curriculum

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Power Management – Need for low power
CMOS basics w.r.t Power Consumption
Low Power Techniques
SoC and PMIC architectures
UPF Concepts
UPF design data flow
UPF Power Intent commands
Memory Controller architecture
Memory Controller low power verification setup
Running low power simulations
How to debug low power issues
Low power assertions and coverage

Course videos

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Unit 1 Low power UPF training agenda 00:02:43
Unit 2 What is power management? 00:27:39
Unit 3 Types of power consumption? 00:20:41
Unit 4 Low power techniques 00:51:52
Unit 5 CLock gating 00:03:02
Unit 6 SOC power architecture 00:42:14
Unit 7 revision 00:21:08
Unit 8 UPF concepts 00:23:11
Unit 9 Functional intent Vs Power intent 00:07:00
Unit 10 state retention 00:46:24
Unit 11 UPF power intent commands 00:52:54
Unit 12 Revision 00:24:53
Unit 13 Memory controller UPF strategy 00:25:19
Unit 14 mem ctrl testbench setup 01:18:23
Unit 15 memory controller power aware simulation debug 01:58:24


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