UVM RAL register model training with hands on project

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UVM Register Model Training

Course Duration : 21+ hours

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About Course

UVM register model(RAL) development training is a 21 hours e-learning course focused on all the aspects of register model development, integration, testcase and checker implementation based on register model. USB2.0 core used as reference design for developing register model, integration and testcase development.


... Register model training include all the aspects of scripting for register model development, front door access, back door access, testcase development, scoreboard logic etc.

Curriculum

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Course videos

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Unit 1 Register model overview, Base classes 02:54:16
Unit 2 Register model development, integration 01:50:32
Unit 3 Ethernet MAC register model development, integration and testcase coding 02:58:30
Unit 4 REGISTER WRITE READ TESTCASE DEBUG, PREDICT METHOD 02:34:30
Unit 5 SPI Master Core Simulation bring up 00:15:00
Unit 6 SPI Core TB Overview, Register sequences description 01:01:30
Unit 7 Register class methods, simulations 02:29:00
Unit 8 Functional coverage in register model 02:33:19
Unit 9 Register build-in sequences for register and memory checking 01:14:00
Unit 10 Creating tests using build-in sequences 01:52:00
Unit 11 USB RAL Model coding 01:02:13


Benefits of eLearning:

  • - Access to the Instructor - Ask questions to the Instructor who taught the course
  • - Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • - Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

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