DMA Controller Functional Verification

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DMA Controller functional verification using SV & UVM

Course Duration : 5 weeks

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About Course

DMA controller is an important aspect of every SOC, which is used for peripheral to peripheral, peripheral to memory and memory to memory data transfers with minimal intervention from Processor. Current DMA controller design has 2 cores with 8 channels per core.


DMA controller functional verification using SV & UVM, covers all the aspects of verification starting from reading the specifications, feature list down, testbench development, testbench component coding, register model development, testcase coding and regression setup, debug for coverage analysis. Course gives indepth overview of sequence development, debugging of complete testcases, etc. Course also introduces to functional and code coverage analysis.


Curriculum

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Feature list down
Testplan development
Functional coverage point list down
Register list down
Testbench architecture definition
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TB component coding
Register model coding
TB component integration
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Testcase development
Register access tests: reset and wr-rd testcases
Functional testcase coding
Test case debug
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Regression setup using PERL script
Regression and coverage report generation
Functional and code coverage analysis
Updating tests for coverage closure
Adding new tests for coverage closure

Course videos

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Unit 1 DMA Spec Session1 03:27:00
Unit 2 SV UVM Advanced Training SES1 03:23:44
Unit 1 SV UVM Advanced Training SES2 01:29:18
Unit 1 SV UVM Advanced Training SES3 02:35:22
Unit 5 SV UVM Advanced Training SES4 03:17:25
Unit 6 SV UVM Advanced Training SES5 03:05:36
Unit 7 SV UVM Advanced Training SES6 03:25:57
Unit 8 SV UVM Advanced Training SES7 03:11:31
Unit 9 SV UVM Advanced Training SES8 03:05:032


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